All Questions
39
questions
0
votes
1
answer
179
views
What are the options to interface Altera or Xilinx FPGA with a microprocessor or microcontroller?
I am trying to design a system which has some sensors connected to an FPGA and want to transfer the sensor data from the FPGA to a microprocessor like NXP IMX. I am new to FPGA and would like to know ...
- 75
1
vote
1
answer
2k
views
How to dump firmware from a PCB with an MCU and FPGA and make sure all data is extracted successfully?
I have an old PCB that is no longer manufactured. I'd like to get the firmware out of it, but it looks like it has an MCU on it and an Altera Cyclone FPGA first generation. I'm still learning how the ...
- 13
10
votes
2
answers
3k
views
RISC-V Zero Instruction Question
I have seen a table of opcodes for RISC-V instructions (for base I 32 bit ISA). I am working with a RISC-V core on FPGA and had BRAM for instructions set to all zeros.
Does anybody know what happens ...
- 1,555
0
votes
1
answer
156
views
Asynchronous read memory causing hold violations in an FPGA
I have a pipelined CPU design in Verilog that uses a memory block whose reads are asynchronous. I have usually had separated memory for instructions and data and everything worked fine, but recently I ...
- 1,259
0
votes
1
answer
568
views
Writing into a full FIFO
I am using a FIFO as a temporary memory block to store values and then perform some calculations between the neighboring values once the FIFO becomes full. After the calculations are finished, I would ...
- 578
1
vote
1
answer
757
views
tRAS definition for DDR memory
In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This ...
- 413
0
votes
1
answer
1k
views
How to Use Addresses with Single Port RAM on FPGA
I am trying to understand this example of single port memory where an 8 by 64 bit RAM is created. If I am understanding correctly, the section of code that says "reg [7:0] ram [63:0]" means ...
- 67
1
vote
2
answers
1k
views
Why do block RAMs have synchronous reading instead of async reading?
I'm programming FPGA boards (Artix 7 to be exact) and I recently noticed that, in order to be synthesized into block RAM, an array of storage must have synchronous reading, otherwise it will only be ...
- 159
5
votes
1
answer
4k
views
why pre-post amble is required?
why do we need pre-post amble for READ or WRITE DQS ?
1 ) one reason could be -->
Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a ...
- 61
1
vote
1
answer
573
views
How to increase memory on the FPGA board?
Situation
I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
- 137
16
votes
3
answers
22k
views
Data Strobe in DDR memory
In DDR3 memory there is a signal called DQS that I have several question about.
What is DQS abbreviated for? specially Q
What is the purpose of data strobe in DRAM and why not use simple clock.
Is ...
- 934
1
vote
2
answers
634
views
Why is there a need for an eNVM and an eSRAM in the same SoC FPGA
SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
- 527
-1
votes
3
answers
793
views
Increase the memory on the FPGA
I would like to run a code on my FPGA (xilinx Zynq zc702)but it got stuck in the middle of the code .
After investigating, I figured out that it must be a memory problem because I am declaring a ...
- 9
3
votes
1
answer
4k
views
Benefits of RAM vs FIFO in FPGA
If I want to process data in the order it arrives, it seems that a FIFO would be most appropriate; however, I want to look over the data multiple times (at least 20 times), so I am considering either ...
- 463
-3
votes
1
answer
478
views
Spartan 6 Internal Memory [closed]
I am referring to below datasheet of IC XC6SLX45-L1FGG484C-ND. As per Digikey portal, it has Total RAM Bits = 2138112
If I want use internal RAM memory is there any specific pins associated with ...
- 739