In this buffer, we have two sections. Let's call these A and B. At one time we write into one but read from the other. So we write into A and read from B, or we write into B and read from A. We can only write into memory if it is empty, i.e read pointer at end. We can only read from memory if it is full, i.e write pointer at end. This means that we either read from a section or write to a section at a time, not both.
In other words, this means that read from a memory section is not possible until that memory section is full. This means that write is not possible until that memory section is empty. In this way, each section A/B stores a whole packet of data.
I created a ping pong buffer using two simple dual port memories. These each have one read port and one write port. The design works. I could extend this to use a single true dual port memory that has two read ports and two write ports. This depends on whether the FPGA and the synthesis tool supports such true dual port memories, which often they do not.
Note: Using two memories means that from an external user perspective, read and write is taking place simultaneously. However, inside the design, one section is either being written (since it was empty) or read from (since it is full).
Now the question is, is it possible to create a ping-pong buffer using a single simple dual port RAM with read and write ports, rather than using two simple dual port RAMs? I have thought about this but can't seem to arrive at a solution. In this case, there will be a single write pointer and a single read pointer. Or I could have two write pointers and two read pointers and multiplex between them.
The problem is that, I can create a simple FIFO from this. However, splitting this into sections A/B and then determining which of these is full or empty is proving difficult. I conclude that such a buffer is not possible using a single simple dual port RAM. But is this true?
