All Questions
38
questions
3
votes
1
answer
82
views
Memory Capacity and Memory Addresses
According to this site, in Table2, HBM(HBM2e) has a capacity of 8Gb = 2^33 bits per channel. Here, it has a 24-bit address consisting of 4 bits from the Bank address BA[3:0], 15 bits from the Row ...
- 33
0
votes
2
answers
118
views
DRAM Memory : How is data stored from the HDD to DRAM? [closed]
When storing data from HDD to DRAM, is one large data block (e.g., 8 bytes) stored in one chip? Or is it distributed among multiple chips in a DIMM? If it is distributed, how many bytes of consecutive ...
- 3
3
votes
1
answer
680
views
In DRAM, why does the precharge operation come after the activate operation and not vice-versa?
Precharging sets the bit line voltage is set to Vdd/2. To read from a dynamic memory cell, the bit line voltage must be near Vdd/2 for the sense amplifier to amplify the data value correctly. Since ...
- 203
5
votes
1
answer
1k
views
Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?
Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
- 203
1
vote
1
answer
567
views
DRAM Refresh Time
I am trying to understand, how can I calculate the refresh time of DRAM, if I consider that as my memory requirement, that I need is 32 DRAM chip of 1M * 1bit each to get 4MB Memory capacity. Each ...
- 13
-1
votes
1
answer
67
views
Instrumentation Tools for Collecting Data in DRAM accesses
We can use instrumentation tools, such as Pin tool, to collect memory accesses of an application running on a system. The type (read or write) and memory address can be collected. How about data? Can ...
0
votes
1
answer
575
views
Calculation of capacitor of deep trench DRAM
If I know the depth of the trench L, the size of the DRAM node D and the thickness of oxide (say HfO2) T. How can I calculate the capacitor of a trench?
- 11
1
vote
4
answers
258
views
What are technical challenges of implementing DRAM memory modules on SBC like Raspberry PI?
I'm surprised to see no Single-Board Computer including Raspberry PI has memory modules for allow for flexible amount of memory (e.g. this review). And I have not found such discussions via web search,...
- 247
0
votes
0
answers
321
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HyperRAM Linear Burst size throughput
Turned out to be a lengthy question, please feel free to skip and go directly to the questions
Intro
I am considering utilizing a HyperRAM in the next design, and studying the datasheet has lead me to ...
- 153
0
votes
1
answer
207
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DRAM cells capacitor operation
I have a question about reading and writing operations.
Say if i wanted to read or write the column WL0, i would enable the WL0 lines.
For either a read of a write i would drive the bit lines to ...
2
votes
2
answers
961
views
Why are DRAM cells laid out in a square with regards to demux size?
I'm reading the chapter about DRAM access (2.1.3) of the paper "What Every Programmer Should Know About Memory - Ulrich Drepper" and there's a certain snippet that I just can't make sense of....
2
votes
2
answers
331
views
How is 1 bit transfered from RAM to a 1 bit register?
I've been reading on computer RAM and CPUs. I came to the conclusion that most RAM today use arrays of DRAM while CPU registers and caches use SRAM. 1 bit DRAM is a circuit with one capacitor and 1 ...
- 121
1
vote
1
answer
342
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DRAM Rank-Level Allocations
I want to do allocations on a specific DRAM rank. The smallest allocation unit in an OS such as Linux is at the page size ...
- 121
0
votes
0
answers
93
views
Termination Requirements for DRAM
I am curious about how to wire DRAM to an SoC. What is required for optimal usage other than the net itself? I have seen conflicting information on if you should or should not use a termination ...
0
votes
1
answer
73
views
Is an even number of DRAM chips required?
I want to design a microprocessor based board (NXP imx 8m). All the boards I've seen so far have an even number of DRAM chips. If I want 4GB of RAM, do I have to use two 2GB DRAM chips or can I use ...
