Questions tagged [ddr3]
The ddr3 tag has no usage guidance.
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Does DDR3 master clock need to be longest trace in general?
I'm working on my first PCB which incorporates DDR3L memory with an STM32MP157AAB3 processor. I've been following ST's DDR3 guide from AN5122 and I came across something which I found odd and which my ...
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Choosing DDR3 for Zynq-7000 (XC7Z010-1CLG400I)
Looking at the AC characteristics of the Zynq-7000 it is said that the maximum data rate of the -1 speed grade is 800Mbit/s (it is also specifically mentioned that the clock frequency for data ...
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
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What does transfer rate in RAM actually mean? How do you actually measure it?
From what I gather, transfer rate is how many bits you transfer via the bus at once with every clock. So the formula would be: frequency (in MHz) * 2 (because of DDR) * bus width (because I think it's ...
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Simulating and verifying DDR3L clock
Context
I am working on a PCB that hosts a Zynq Ultrascale+ SoC and has 9 DDR3L SDRAMs (MT41K512M8DA) operating at 1866Mbps, and I have to verify the signal integrity of the DDR3L interface. I am ...
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DDR pin swaping why D0, D8, D16, D24, D32, D40, D48, and D56 are fixed
Below image is taken from Hardware Development Guide
for i.MX 6SoloLite
Applications Processors.
You can see that in each byte lane first and last bit are fixed.You are not allowed to swap.
May I know ...
- 2,593
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how to make length rule for one net shorter than other (DDR3)
I am doing layout for a DDR3 (1333MHz speed type).
In the layout guideline of the processor it sayst that the adress/controll signals needs to be 40 picoseconds shorter than the CLK signal.
Is is ...
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Implementing DDR In/Out DQ Pin for DDR3 SDRAM on Xilinx Spartan-6 FPGA
I’m currently working on a project that involves interfacing a DDR SDRAM (Micron MT41J128M16) with a Xilinx Spartan-6 FPGA. I have implemented a controller. I’m looking for guidance on how to properly ...
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DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
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Why is there a tRRD in DDR3? There does not seem to be a resource conflict between different banks
In DDR3, bank activation is specific to the Bank, for different banks, they all have their own sense amp and do not seem to affect each other, so why would there be tRRD?
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Is there any chance to configure DDR3L SDRAM on Digilent Arty A7 FPGA development board to Dual Channel memory?
There are 256MB DDR3L SDRAM installed on Digilent Arty A7 FPGA development board. Dual Channel memory is popular nowadays in a PC. So I was wondering if there is any chance to configure the DDR3L ...
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Why is the DDR termination voltage half the supply voltage? [closed]
Why is the DDR termination voltage (VTT) one-half the VDD voltage?
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Drive strength and impedance
I have a custom embedded board with an MPU (i.MX6ULL) interfaced to a DDR3L. After noticing occasional hangs and crashes, I started tinkering with the DDR Drive Strength settings and was surprised how ...
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Why is the burst order of DDR3 DRAM not sequential?
Based on the JEDEC DDR3 documentation as shown below, when we are reading with burst length of 8 and starting column address of 010 (0x2), the burst order will be <...
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Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?
Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
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