All Questions
22
questions
3
votes
1
answer
238
views
How can I improve this RAM implementation in VHDL?
I'm practicing for a lab exam and I'm trying to solve one from past years. I feel like I'm doing something wrong because I don't have much experience with VHDL.
Exam question
Write the VHDL code for ...
-1
votes
2
answers
94
views
Bistable memory cell with paired buffers instead of paired inverters
Bistable memory cells with paired inverters are very standard and basic building blocks (was used in Intel 8086 for example. ) But why not use paired buffers instead?
1
vote
2
answers
217
views
Is my understanding on flip flops accurate?
I have done a lot of research on flip flops so to speak and I have put together my understanding, please correct were I’m wrong.
Flip flops are bistable multivibrators able to store two states (one ...
7
votes
6
answers
1k
views
Why are flip-flops criss-crossed?
I want to simulate how a computer works using logic gates. Right now I am trying to build the memory aspect of it.
After looking at various articles and books I see a lot of them using flip-flops/...
1
vote
2
answers
210
views
Non volatile memory on simple hardware board [duplicate]
I'm designing a low frequency board with some analog signals inputs and a few discrete logic gates which drive warning LEDs. I want to save the status of the LED even if the board is powered off. No ...
0
votes
0
answers
55
views
Advice on SIPO FIFO clock, as well as 555 timer usage
I've made a circuit which involves me entering inputs, and the result being displayed in a seven segment LED. The LED must flash on and off and display the input number at least two times in two ...
0
votes
1
answer
76
views
Shared rising edge detector? [closed]
Why do we have a rising edge detector in every flip flop of a register. Can't we just make a shared one for all the flip flops in order to save hardware?
0
votes
1
answer
338
views
Logism: Rising-Edge J-K flip-flop outputs 0 when J = 1 and K = 0 [closed]
According to the truth table of the J-K flip-flop:
When J = 1, K = 0, and CLK (Clock Signal) = 1, Q = 1.
FYI, the flip-flop is a Rising-Edge flip-flop. Below are the timing diagrams which show the ...
1
vote
1
answer
77
views
Trouble Storing Information in D Flip Flop
So I'm really not understanding how to store bits in flip flops and have them enable for to change on a condition. Here's the general setup that I'm trying to do but it just doesn't seem to work.
1
vote
0
answers
22
views
Recover correct value from unstable memory through read operation
We are given a memory with 32-bit width for each word. it has the length (N - number of rows) which is not relevant for the question. we know that the memory has a problem where at any row, one bit ...
0
votes
2
answers
285
views
What is the relevance of a !Q in the D Flip-Flop when using for a memory module?
If the purpose of this circuit is to store the value of D in Q, why should I need a !Q? Why don't use a circuit like this instead?:
1
vote
0
answers
46
views
Devices storing volatile memory
I've hit a bit of a rut in a question on my homework for my computer architecture class (MIPS architecture):
what are digital logic devices that can implement 1 bit and 32 bit volatile memory, and ...
1
vote
1
answer
853
views
Design this memory with D flip-flops
Design the following memory with D flip-flops (you can use other gates or decoders if needed).
The following memory has 4 one-bit locations and can access 2 locations at each moment and read from ...
0
votes
1
answer
117
views
Memory in sequential circuit
In sequential circuit block diagram ,it is said that some outputs are again feedbacked to inputs,after storing them in memory.
But,where is that memory in sr latch.In sr latch ,it is seen that the ...
0
votes
2
answers
127
views
Question on flip-flops
I came across a question which says the following,i don't understand the question and how to come up with a solution
In fig,the data word to be stored is S=1001
a)If LOAD is LOW,what does Q equal ...