Questions tagged [ram]
RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.
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FPGA Block RAM: Does Read Enable being low save power?
I am trying to understand the actual purpose of the read-enable signal on synchronous FPGA Block RAMs. I do not see the actual need of it.
But regardless of why it was put there in the first place, ...
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What does transfer rate in RAM actually mean? How do you actually measure it?
From what I gather, transfer rate is how many bits you transfer via the bus at once with every clock. So the formula would be: frequency (in MHz) * 2 (because of DDR) * bus width (because I think it's ...
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Is the communication between memory controller and RAM serial?
I used to think that the communication between memory controller and RAM is parallel since we know that a RAM stick has multiple pins, just like this:
But then, from Wikipedia article on memory ...
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4-bit IC to 8-bit RAM module
I'm trying to wire up a RAM module based on the Ben Eater's RAM Module Part 1 video, but there are no available RAM chips where I'm located at so the only IC I have available is a CAT22C10 NVRAM which ...
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DDR Data strobe wiring
I have a device that has a unified memory architecture and has four 32bit ddr ram chips totaling 128bit and only has a single data strobe for the whole 32bit address bus on each chip not for each byte ...
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How to test for stack overflow on an ATtiny85 using an emulator?
I am developing a hobby project using the Arduino IDE and an USBasp programmer to upload my code to the ATtiny85. After programming, I remove the chip from the programmer socket and put it into the ...
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Connecting higher density LPDDR3 SDRAM than the ATSAMA5D27C processor supports
I'm designing a Single Board Computer for the first time. The board will have ATSAMA5D27C as its MPU with LPDDR3 SDRAM. The datasheet specifies that the maximum SDRAM it can support is of 4Gb (512 ...
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For DDR4 and DDR5, is tCCD_l timing to be obeyed for accesses in a single row as well?
So I have been trying to learn about DDR4 and DDR5 memories, and it seems that the Column-to-Column delay values (in clock cycles) are different depending on whether consecutive accesses are inter-...
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What is the theoretical maximum capacity of 72-pin RAM modules?
I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect.
This is my current understanding:
A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For ...
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DS1220 vs X2816A
I have a legacy device from 1996 that uses a Dallas DS1220 NV RAM. The battery is shot and the device won't even boot. But if I swap in 6116 RAM chip, it comes up and works but of course won't save ...
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Why do STM32 MCUs divide RAM into SRAM1 and SRAM2?
Why do STM32 MCUs divide RAM into SRAM1 and SRAM2? They seem contiguous, so that I could simply configure my linker to treat both as just one chunk of RAM.
Should I do that? If not, how do I tell the ...
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MUX in a 4 bit by 3 bit memory
Here is a 3-bit adressable memory with an adress space of 4.
My question is why is the book calling the 3 rightmost highlighted circuits MUXes? And what type of MUXes are they? 4:1 MUX? And if it is ...
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Calculate Memory Address
I know this is a simple arithmetic question for many of you, but I can't figure out how to solve this problem.
In a uController (this is an example, it doesn't matter which one) SRAM1 has ...
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Ideas about generating images for E-Paper display
I am currently working on a project where I'm using a DA14531 BLE-module to collect data from some sensors and display the collected data on an E-paper display. As the display is quite large (400x300 ...
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PIC18 Bit-addressable RAM
Given that the PIC18 architecture does not provide any bit-addressable RAM, would it be a sane idea to utilize carefully considered unused bit-addressable SFR's? For example, if my project does not ...
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