All Questions
47
questions
0
votes
0
answers
53
views
Weird SRAM failures when heat is applied to the system and when probed
I'm providing assistance on a project that is encountering some interesting behavior on an SRAM memory device when environmental temperature goes up or when someone probes/touches lines associated ...
- 107
7
votes
2
answers
2k
views
What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?
I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
- 73
1
vote
1
answer
136
views
Bitline is not working correctly (6t cell sram with sense amp and precharge)
After simulating 6t ram with sense amplifier and precharge, bit line value is fixed to 1.5v. How can i avoid this? Using pspice to simulate.
0
votes
2
answers
167
views
Clarification about Memory Address
I've been working with a project regarding an SRAM Controller in Verilog. As you can see, my controller should include those blocks. I've written some Verilog Code and right now I'm trying to test it, ...
5
votes
3
answers
813
views
How to write to a Hitachi HM628128A SRAM?
I'm working with a Hitachi HM628128A SRAM chip.
According with the datasheet, the function table is
How do I write data in the chip? Must I execute "write cycle (1)" and then "write ...
- 209
8
votes
4
answers
4k
views
Why does this SRAM chip have more physical bits than declared by the manufacturer?
I noticed while scanning the datasheet for a 23K256 SRAM chip that it has 32768 bytes (+262Kbit.)
The manufacturer clearly identifies this chip as 256Kbit.
Reading through the datasheet it clearly ...
- 199
0
votes
1
answer
84
views
Externally triggered high impedance toggle for large number of parallel lines
First, I want to apologize for my terminology here -- I'm a software engineer rather than EE and I'm a bit rusty.
I have a parallel SRAM chip that is being shared by 2 CPUs that requires 19 address ...
- 131
0
votes
0
answers
60
views
Do SRAM Macros register the inputs?
In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file).
My question is this: SRAMs ...
- 143
0
votes
2
answers
1k
views
SRAM: Purpose of Upper and Lower Byte Enable when Data Bus is greater than 8-bits?
What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits?
Is it related to multiplexing? I had always assumed that SRAMs were either designed with either ...
- 56.9k
0
votes
3
answers
251
views
External Memory IC which increments data on a clock pin
I am searching, with no success, in multiple categories of the external memory IC market for a chip that can do the following:
Store 1MB of data of 16-bit data
This data is stored at specific ...
- 361
0
votes
0
answers
95
views
If the Sense Amplifiers structure is the same as an SRAM cell's, why the differential voltage on the bit line gets amplified?
source
How you can see the structure with 6 transistors of a Sense Amplifier (SA) is the same as a SRAM cell, but this latter causes a little variation on the bitline voltage that the SA will amplify....
- 121
1
vote
1
answer
71
views
External bus interfacing
This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
0
votes
1
answer
81
views
How do I produce WE in this diagram?
I have designed a memory system that has 10KB ROM followed by 6KB of RAM. The ROM begins at 0000H. I had to use two 4K x 8bit ROMs and one 2K x 8 bit ROM. I also have to use one 2K x 8bit RAM and a 4K ...
user170589
2
votes
3
answers
642
views
Interfacing 16-bit SRAM/MRAM with Arduino Mega
I a looking to interface a MR2A16A 4 Mb 16-bit MRAM with an Arduino Mega. I am new to interfacing with memory chips and would like some advice from someone more experienced than myself. I am not ...
0
votes
2
answers
339
views
Maximum cells in a row in a SRAM memory array
I was considering designing an SRAM memory array. For my design to be useful in a certain system, I need to have several cells in a row (e.g. 1024, 2048).
In textbooks I have seen examples of arrays ...
- 3