Skip to main content
Electrical Engineering
EquipDev's user avatar
EquipDev's user avatar
EquipDev's user avatar
EquipDev
  • Member for 9 years, 3 months
  • Last seen more than a week ago
Profile Activity
Stats
579
reputation
38k
reached
5
answers
23
questions
Communities
View all
Badges
View all badges
This user doesn’t have any gold badges yet.
6
silver badges
15
bronze badges
Top tags
View all tags
2
Score
6
Posts
21
Posts %
1
Score
7
Posts
25
Posts %
1
Score
3
Posts
11
Posts %
1
Score
2
Posts
7
Posts %
0
Score
10
Posts
36
Posts %
0
Score
3
Posts
11
Posts %
Top posts
View all questions and answers
9
Can continuity test cause component damage?
Jun 6, 2020
8
Is a multimeter with 1,200,000 counts actually a 6½ digit multimeter?
Dec 23, 2018
8
Is there a standard way over JTAG to program a flash connected to an FPGA?
Feb 25, 2022
3
How to specify a minimum clock to output time in output timing constrain?
Mar 30, 2016
3
What is the difference between DCM and PLL in e.g. Xilinx FPGA?
Nov 16, 2016
2
Why does FPGA PCI Express Tx output have on-chip termination of 100 Ohm?
Jan 12, 2021
2
How to ignore simulation only ports when mapping to FPGA pins?
May 20, 2021
2
What value to use for Byte Count field in PCI Express (PCIe) IO read completion?
May 25, 2021
2
How to monitor Ethernet packet loss real time on different connections?
May 7, 2022
1
How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?
Aug 12, 2019
Top network posts
View all network posts
196
How to get absolute path of a pathlib.Path object?
31
How to compare two files as part of unittest, while getting useful output in case of mismatch?
31
How to calculate length of string in pixels for specific font and size?
29
Hotkey for next song in Spotify
21
How to save pillow image object to Django ImageField?