Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (tCCD_l).
From Micron Brief of DDR5 SDRAM:
Bank-group-to-bank-group interleaved timing accesses are shorter than bank-to-bank within a specific bank group access. These timing parameters have “long” timing definitions (tCCD_L, tWTR_L, tRRD_L) and “short” timing definitions (tCCD_S, tWTR_S, tRRD_S). The long timings refer to bank-to-bank within a bank group, while the short timings refer to accessing different bank groups
My question is: what is the access latency of sequentially accessing columns WITHIN a single bank. To be clear: do not change the row, do not change the bank-group OR the bank, just access the next 8n or 16n words from the same bank.
Is it equal to tCCD_l because I am accessing within the bank-group?
Or is it tCCD_s because I am not going bank-to-bank?
To me, the latter makes sense, since we do not need to switch to another bank within the bank-group. If I am wrong here, what is the reason for that?
