Questions tagged [ddr]
Double Data Rate describes a computer bus that transfers data on both the rising and falling edges of the clock signal. Often used to describe SDRAM access.
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IBIS File pin Matching
STM32MP153CAA3
I will make pin mapping for ibis LPDDR2 CK enable pin for STM32MP153CAA3. Which one should I choose among the model selector options?
Which characteristic impedance should I choose for ...
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Benefit of bank groups in DDR4 and beyond
I'm trying to understand how grouping the banks together can increase the throughput of DDRx. Reading into the sense amplifier appear to be the main bottleneck in DDRx throughput, however there is ...
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
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How can autorouting be done in Altium CircuitMaker?
I need to do autorouting in Altium CircuitMaker. I have only found information how to do autorouting in Altium Designer.
What I need to know is to set up rules and enviroment for autorouting with the ...
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What is the DDR4/5 Colum-to-Column access latency for within bank access
Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
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DDR3 U-DIMM Signal Reference Plain
I am doing the PCB layout of a DDR3 U-DIMM and I have run into a perceived gap in the JEDEC DDR3 DIMM standards and am hoping to get some input from a DDR3 SME who could clarify the Address/Control ...
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DDR Data strobe wiring
I have a device that has a unified memory architecture and has four 32bit ddr ram chips totaling 128bit and only has a single data strobe for the whole 32bit address bus on each chip not for each byte ...
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Picking the best memory technology for our needs
This is my first post here, but bear with me. I have come here after searching the internet for a while (like most of us do)
We are in the process of figuring out which memory option would be the best ...
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Connecting higher density LPDDR3 SDRAM than the ATSAMA5D27C processor supports
I'm designing a Single Board Computer for the first time. The board will have ATSAMA5D27C as its MPU with LPDDR3 SDRAM. The datasheet specifies that the maximum SDRAM it can support is of 4Gb (512 ...
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What is the fastest achievable output speed for an FPGA?
To sum up the question, I would like to know what is the maximum frequency with which I can toggle an output of an FPGA. I do not intend this question to be specific to any particular board or vendor. ...
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DDR pin swaping why D0, D8, D16, D24, D32, D40, D48, and D56 are fixed
Below image is taken from Hardware Development Guide
for i.MX 6SoloLite
Applications Processors.
You can see that in each byte lane first and last bit are fixed.You are not allowed to swap.
May I know ...
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What is the definition of DDR memory latency?
On Corsair's web site, they define memory latency with an equation:
(Real Latency) = CAS Latency x 2000 / Data-rate
My question is what that means in practice. Is this the delay from the time the ...
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For DDR4 and DDR5, is tCCD_l timing to be obeyed for accesses in a single row as well?
So I have been trying to learn about DDR4 and DDR5 memories, and it seems that the Column-to-Column delay values (in clock cycles) are different depending on whether consecutive accesses are inter-...
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DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
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What are the options to interface Altera or Xilinx FPGA with a microprocessor or microcontroller?
I am trying to design a system which has some sensors connected to an FPGA and want to transfer the sensor data from the FPGA to a microprocessor like NXP IMX. I am new to FPGA and would like to know ...
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