Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
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Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?
Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
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SDRAM interfacing problem with lpc4357
I am trying to interface SDRAM - AS4C8M16SA from Alliance, with LPC4357 (LQFP208 package). I'm not familiar with EMC or SDRAM. I got the RAM get initialized. But ,I cannot successfully write beyond 64 ...
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How to know the memory occupied by the various memory segments in a microcontroller
I'm using STM32 based microcontroller, IAR embedded workbench and STlink v2 debugger. I just want to know how to check the memory utilized/used by the program/system in various memory segments like:
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How to verify if SDRAM alternative is a direct drop in replacement?
I'm trying to verify whether the two SDRAM chips are complete drop in replacements of each other. I've verified the footprint, electrical characteristics and various timing parameters (namely CL, tRCD,...
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DDR3 SODIMM slow clock specification
I am considering to design memory controller handling 1GB of the RAM. I did already design controller for Micron's 32MB SDRAM in the past using Cyclone III device.
The new design is for retro ...
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Interfacing NAND flash with USBMSD
I'm trying to read files from a NAND flash (K9LAG08U0M) that I took off an old MP3 player, so far I've been able to read the NAND contents successfully by interfacing it to my PC as a USBMSD (Mass ...
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Does NOR flash wear occur when rewriting a bit to its same value?
The obvious answer is no. Wear is caused by discharging a memory cell (bit). If the cell is a 1 and you write a 1, the cell does not get discharged. If the cell is zero and you write a zero, the cell ...
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DDR4 Routing Consideration
I'm designing a new PC based on Intel Tiger Lake UP3.
In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2).
each BO has different impedance ...
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eMMC Jedec Backward Compatibility
I'm working on a new design based on a Xilinx FPGA.
I'd like to use some eMMC devices but the FPGA controller supports JEDEC up to 4.51.
Nowadays, some eMMC devices are JEDEC 5.0 or 5.1 compliant ...
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How is it possible that lower CAS latency and lower timings on RAM memory to result in lower performance?
I have watched many benchmarks on RAM memories and I was shocked to find out that sometimes lowering the memory timings can result in lower performance in BOTH synthetic benchmarks general use of ...
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Problem with writing eeprom memory
I am trying to write atmel at28c256 on breadboard so I tied all address lines to ground, and all I/O lines also tied to ground. I untie I/O lines for reading, tie 'WE to high, 'CE to low, and 'OE to ...
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Best device to read/write memory on multiple architectures?
tl;dr: I want to read/write memory from a PIC MCU and an EEPROM, both of which are soldered to an experiment board. I would like to explore programming and debugging ARM in the near future. Which ...
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Why DDR3 RAS timing have to be greater than RCD + CAS timing?
By definition, tRAS is the minimum delay from when a particular row in a bank is activated, to when it can be closed with a PRE command.
I have seen claims numerous times that tRAS should be > tRCD + ...
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STM32 Flash acting like RAM
I've been trying to program a word of flash memory on my STM32F030F4, but for some reason whenever I power it off and on again, the memory location has defaulted to '0xFFFFFFFF' again. Am I missing ...
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Creating ping-pong buffer using a simple dual port RAM
In this buffer, we have two sections. Let's call these A and B. At one time we write into one but read from the other. So we write into A and read from B, or we write into B and read from A. We can ...
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