All Questions
Tagged with memory microprocessor
39
questions
0
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1
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84
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eMMC interfacing with EC200U SDIO Power domain
I need to interface my eMMC(THGBMJG6C1LBAU7) memory with EC200U from Quectel.
The Quectel E200U has two SDIO ports one is working at 3.3V power domain and
other one is working at 1.8V power domain.
...
0
votes
1
answer
65
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Tsi107 PowerPC Host Bridge Vs Processor
I a confused regarding the difference between a powerPc host bridge and a processor. According to the host bridge datasheet, it can be programmed, and it has interrupt generation and handling, and ...
0
votes
1
answer
179
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What are the options to interface Altera or Xilinx FPGA with a microprocessor or microcontroller?
I am trying to design a system which has some sensors connected to an FPGA and want to transfer the sensor data from the FPGA to a microprocessor like NXP IMX. I am new to FPGA and would like to know ...
0
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0
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366
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Error after flashing the example on my esp32-c3 board
I am currently trying to develop software for a board I created a short time ago with the esp32c3 as microprocessor.
I followed all the steps of the espressif 'get started'.
I firstly set the ...
1
vote
0
answers
26
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DDR interfacing with rockers3399 processor
I am using rockers 3399 processor in one of my applications. if you see page no 9 'External Memory or Storage device' section you can see the below things
*Support 2 channels, each channel is 16 or ...
1
vote
1
answer
340
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Is the following 8085-based design I/O mapped or memory mapped?
The above picture is an 8085-based system schematic used for undergrad courses at the laboratory. Now at first sight it seems that the 8085 in the circuit is isolated mapped IO since it uses the IO/M' ...
0
votes
2
answers
368
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Difference between ARM7 and intel i3, i5 & i7 processors
I am just starting out on a journey to understand microcontroller and microprocessor design. Have read briefly on their differences (ARM7 and Intel i3, i5 & i7).
Couldn't find any information on ...
0
votes
1
answer
87
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How does this expanded memory bus work?
I'm reverse engineering a laser printer (Laserjet 1320) and I need to infer some things about the memory bus. The full schematic I've made while reversing is here (in pdf) on Drive. I'm not all that ...
0
votes
1
answer
73
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Is an even number of DRAM chips required?
I want to design a microprocessor based board (NXP imx 8m). All the boards I've seen so far have an even number of DRAM chips. If I want 4GB of RAM, do I have to use two 2GB DRAM chips or can I use ...
2
votes
4
answers
2k
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Memory Mapped IO and IO Mapped IO
I am revisiting Microcontrollers and Microprocessor concepts.
Yes. I know this question has been asked many times like here and here. I have also visited many sites regarding this concept but still I ...
0
votes
2
answers
1k
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Memory-mapped IO vs Port-mapped IO in microcontrollers
I've been reading about external peripheral mapping to microcontrollers.
I understand that memory-mapped IO means that the same address space in the microcontroller can be used for internal memory ...
0
votes
2
answers
722
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Data Bus and High Impedance
Let's consider an interface between a simple microprocessor and a certain memory. For instance, let's assume that the microprocessor drives the address bus, a read signal, a write signal, and that the ...
-1
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2
answers
71
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Data transfer from/to memory [closed]
Consider an interface (between a memory and a processor, or between a memory and an ASIC, or similar situations) in which there is a data bus of 8 bit. Suppose I want read a 16 bit data from memory, ...
1
vote
1
answer
71
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External bus interfacing
This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
0
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1
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544
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Is a multiplexer needed to read from memory
we need to enable a register to write into that register, which is done using a decoder.
even if we enable 1 register using decoder, given that RD(bar) is 0, all registers can still produce an output. ...