Questions tagged [yosys]
Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.
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What/why are the patterns in the "unused" portion of this ASIC?
The below image is a 150um x 170um block from an ASIC design file produced automatically by fully open-source tools such as yosys.
The apparently unused sections have a repetitive pattern, presumably ...
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What is Warning: Replacing memory \MEM with list of registers?
I have this little code that displays a binary count on LEDs:
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Support for ICE40UP5K-SG48I in IceStorm?
I hope this is the correct place for IceStorm questions ..
The IceStorm website shows support for,
iCE40-UP5K-UWG30
The Single Wire Aggregation Demo / Development Board from Lattice
uses a Different ...
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Nextpnr unconstrained error
I am trying to build a clock divide chain on an iCE40 UPduino card and have run into a problem with nextpnr. I've minimized a working / non-working example. This code works:
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Synthesizing designs in yosys [closed]
If you have a sequential circuit in verilog or system verilog and want to synthesize it to specific gate types and flip-flops, how do you go about it. For example, may be synthesize the design to nor,...
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Why does yosys mark used sub-modules as unused?
Question:
Why does yosys mark used sub-modules as unused?
Background:
I am trying to find a rough estimate of the area of a circuit. Some years ago, during my bachelor's, I have used a synthesis tool. ...
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SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops
Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...
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ice40-hx8k: Weird input pin behaviour regarding digital HI voltage level
I am playing around with a FPGA dev board featuring the Lattice ICE40-HX8K using the yosys/icestorm OpenSource toolchain, and I have noticed very odd behaviour my input pins are showing:
When I use a ...
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Why is this Verilog RAM modification better in terms of resource usage?
I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
