All Questions
4
questions
0
votes
4
answers
245
views
Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?
There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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1
vote
1
answer
146
views
SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops
Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...
6
votes
1
answer
930
views
Latches and Two Phase Clocking in modern ASICs
Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
user105000
0
votes
1
answer
272
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set and reset of D flip-flops : always physically present?
On various technology (discrete, ASIC, FPGA), I'd like to know if the asynchronous signals set and reset are always present on D (edge-triggered) flip-flops. If not how the reset process can be ...
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