All Questions
Tagged with asic physical-design
4
questions
0
votes
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Standard cell design flow in an ASIC design flow
I have a question regarding the standard cell design flow in an ASIC design flow.
That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured ...
- 103
1
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Calculating resistance for metal layer from LEF File
I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278.
In the File description it is written as ...
3
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2
answers
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Please explain tech.lef , tech.lib
Can anyone explain what is in the tech.lef and tech lib files? Which stage of PNR (Place and Route) are they used for? Are ...
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What are the general steps used in creating a ASIC?
I'm following a discussion board that discusses an ASIC chip they are building, and they are using terms that I'm unfamilliar with. So far I've gathered
Once a logic design is tested on an FPGA it ...
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