All Questions
12
questions
0
votes
1
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68
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What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
- 137
0
votes
1
answer
698
views
Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule
I have an issue in timing slack got from Design Compiler (DC.)
One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
- 17
1
vote
2
answers
1k
views
Does it make sense to use a clock input for combinational logic?
Today, I came across this problem on QuickSilicon's RTL Hackathon. It was to design an Endian converter.
The requirements were
The output should be available in the same cycle
The module should ...
- 2,331
1
vote
1
answer
7k
views
How to implement Clock Gating Style RTL into synthesis?
I'm studying to implement a Clock Gating in RTL.
So I've followed as the below
https://www.design-reuse.com/articles/23701/power-analysis-clock-gating-rtl.html
...
- 619
0
votes
1
answer
73
views
FSM modeling when outputs are not simple functions of input and current states
All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...
- 74
0
votes
1
answer
243
views
Respecting setup/hold time in RTL design
This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals.
In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
0
votes
0
answers
1k
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Finite state machine to detect if a number is divisible by 5 if LSB comes first [duplicate]
If MSB comes in first, we can keep track of the remainder for each new bit since the additional bit will either cause the number to be 2x or 2x+1.
But if LSB comes in first, how can we come up with ...
- 1
7
votes
1
answer
797
views
High-Level Synthesis (HLS) vs RTL for ASIC flow
I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
- 71
1
vote
2
answers
2k
views
Why aren't latch based designs common these days?
Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
- 682
0
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1
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308
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Some question about RTL Design and VHDL
I have some question almost uncorrelated, so I'll enureamted it, hope you can help me:
1) I'm studing RTL Design, and the question is at level of data path, arithmetic unit ecc. I don't understand ...
- 143
0
votes
2
answers
5k
views
How to find high fanout nets?
In the timing report of a synthesis with Synopsys VCS, a warning states:
Warning: Design contains 8 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these ...
- 146
4
votes
3
answers
392
views
Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?
I am synthesizing some multiplication units in Verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using Booth Encoding when ...
- 203