All Questions
65
questions
0
votes
1
answer
48
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Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
0
votes
1
answer
104
views
How to do clock signal rising edge detection in Chisel (scala)?
I have encountered in a problem of rising edge detection in writing chisel code. Here is the code I wrote.
...
- 21
11
votes
5
answers
3k
views
Can we say that a CPU is an ASIC that is designed to perform a wide range of instructions?
My question is more terminological than technical.
I have come across different definitions of what an ASIC is. The most common one is that an ASIC is an IC that is designed for a specific application ...
- 139
0
votes
2
answers
109
views
Can a digital system be considered an ASIC regardless its physical implementation?
From my knowledge from classical books of computational and digital systems, an ASIC is a category of full-customized or semi-customized integrated circuit (IC) tailored to a specific application.
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- 207
0
votes
2
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315
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Are SR latches bad in ASIC design?
I am implementing an ASIC design, and my current solution for a problem requires an SR latch. I've always been told that latches are bad in FPGA and ASIC designs, but never got a proper answer as to ...
- 103
1
vote
1
answer
46
views
What is name of the technique where we create modules to help us test our digital design?
In my FPGA design project, I created a few modules that can be used to emulate output from another module. Then there were modules that would inject erronous data or signals that signify errors. By ...
- 12k
4
votes
2
answers
739
views
Why don't 2 flip-flop synchronizers have a reset?
This is similar to this question, asking if a reset is needed in a 2 flip-flop synchronizer. The answer to that question was: "no, not necessarily".
So, my question is:
Why do almost all of ...
- 280
2
votes
2
answers
480
views
Why is a reset with asynchronous assert safe?
As far as I understand, a reset with asynchronous assert, synchronous de-assert is considered absolutely safe. I understand that this prevents metastability at the output of a flip-flop using that ...
- 280
2
votes
3
answers
930
views
Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?
There are several techniques that can be used to transfer data between two asynchronous clock domains. For a few bits, and depending on direction of data between the two clock domains, one could use ...
- 12k
1
vote
1
answer
128
views
8bitworkshop(verilog) to terminal transition
I have been working through very basic Verilog code examples at https://8bitworkshop.com (supports a book I am following). I understand there are a few good online options available and will pursue ...
5
votes
3
answers
2k
views
How is clock gating physically achieved inside an FPGA or ASIC?
It is bad idea to add logic gates in clock signal path. How is clock gating achieve in FPGA and ASIC designs and how does it prevent glitch in the output signal i.e the gated clock as it is enabled or ...
- 12k
3
votes
2
answers
517
views
Does the term micro-architecture have a meaning outside of microprocessors?
Wikipedia defines microarchitecture as follows:
In computer engineering, microarchitecture, also called computer
organization and sometimes abbreviated as µarch or uarch, is the way a
given ...
- 2,103
10
votes
3
answers
2k
views
How were custom chips designed in the days prior to the arrival of FPGAs as hardware emulation devices? [closed]
One of the applications of FPGAs is to model a computer system/chip/functionality on it prior to mass manufacturing the copies of finalized design. How was this done before FPGAs were used for this ...
- 565
2
votes
3
answers
2k
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Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?
Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?
- 413
0
votes
3
answers
345
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What is the difference between "2 synchronize" and "metastability"?
As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below,
cross clock domain databus
But I came across about ...
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