All Questions
5
questions
6
votes
3
answers
227
views
Behaviour of uninitialised RAM in an ASIC
This is a question for anyone with experience designing or with a deep knowledge of volatile memory in an ASIC. E.g. chip designers or silicon process engineers.
We are using the ET1200 EtherCAT ASIC (...
- 27.5k
0
votes
1
answer
68
views
What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
- 137
0
votes
0
answers
60
views
Do SRAM Macros register the inputs?
In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file).
My question is this: SRAMs ...
- 143
0
votes
1
answer
85
views
What is the delay incurred by ternary content-addressable memory (TCAM)?
What is the cost (in terms of delay) of using TCAM? How do they compare with SRAM and DRAM?
I understand their use cases are different. But assume, for an application, I can do an operation using ...
0
votes
1
answer
189
views
Baseband Processor
If a device can only be activated by way of RF then I would tend to believe that the BB processor (embedded via ASIC design) would need to be active and powered on yes ? If correct then does it have ...
- 221