All Questions
4
questions
1
vote
0
answers
440
views
Power analysis using Synopsys Design Compiler
I am trying to generate power report using Synopsys DC compiler.
At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command.
Then I ...
- 11
0
votes
1
answer
243
views
Respecting setup/hold time in RTL design
This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals.
In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
4
votes
2
answers
776
views
how slow are modelsim free licences?
I know in free licenses of modelsim / questa simulations run slower than the full version.
But how slow? will it be 2x 3x 10x faster in the paid version?
what about actel/microsemi free version ?
3
votes
1
answer
4k
views
Aggregate of 2 vectors in VHDL
I am checking what I can and cannot do in aggregating and concatenating in VHDL.
while I can combine two vectors by concatenating them, I keep getting error if I use aggregate.
I saw one answer here ...
- 305