All Questions
Tagged with asic timing-analysis
14
questions
0
votes
1
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727
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Pin vs Port terminology in SDC
In SDC (Synopsys Design Constraints), set_driving_cell is said to be used to model the drive resistance of the cell driving the input port. I'm confused by the word ...
- 1,074
4
votes
2
answers
739
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Why don't 2 flip-flop synchronizers have a reset?
This is similar to this question, asking if a reset is needed in a 2 flip-flop synchronizer. The answer to that question was: "no, not necessarily".
So, my question is:
Why do almost all of ...
- 280
2
votes
2
answers
480
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Why is a reset with asynchronous assert safe?
As far as I understand, a reset with asynchronous assert, synchronous de-assert is considered absolutely safe. I understand that this prevents metastability at the output of a flip-flop using that ...
- 280
0
votes
3
answers
345
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What is the difference between "2 synchronize" and "metastability"?
As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below,
cross clock domain databus
But I came across about ...
- 619
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1
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698
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule
I have an issue in timing slack got from Design Compiler (DC.)
One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
- 17
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4
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245
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Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?
There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
- 1
2
votes
3
answers
2k
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Multiple Reset Synchronization
I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
- 697
1
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2
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3k
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How to constrain a clock signal out from a multiplexer
How would you constrain this design?
ext_clk and clk_in are asynchronous to each other.
clk_div is derived by clk_in with double period.
clk_out may be driven by either clk_in and ext_clk, ...
1
vote
2
answers
1k
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Edge aligned Source synchronous outputs
This is a basic block diagram of source synchronous interface I found in altera document.
Here
This is how edge aligned source synchronous output looks like.
They say the reciever will shift the ...
- 2,772
3
votes
1
answer
704
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Timing Constraints
I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
- 11k
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2
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2k
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How does asynchronous and synchronous reset signal affect the setup and hold time in a Flip Flop?
Does the async. and sync. reset signal follow the setup and hold time conditions of flip flop? If so how would they affect the output?
- 137
4
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1
answer
2k
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Advantage of clock enable over clock division
I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
- 883
0
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2
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5k
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How to find high fanout nets?
In the timing report of a synthesis with Synopsys VCS, a warning states:
Warning: Design contains 8 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these ...
- 146
0
votes
1
answer
169
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data bus power consumption
In a design I have, I am using a memory arb (receiving mem requests from two masters) What are the pros and cons for each of the follwing:
use a mux for the read data of each master, so that if the ...
- 1