All Questions
7
questions
1
vote
2
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2k
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Why aren't latch based designs common these days?
Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
2
votes
2
answers
477
views
How is the bias current reference value determined for CMOS circuit design?
In the few textbooks I'm reading on CMOS analog design, they all seem to have reference currents of \$10 \mu A\$ or similar that get mirrored, and there doesn't seem to be any discussion on how this ...
0
votes
4
answers
4k
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In CMOS, can I assume the delay of a multiplexer is negligible compared to the delay of an inverter?
Let say I have a ring oscillator, and I modify the ring so that the output of an inverter is connected to an input of a 2-to-1 MUX, and the output of the MUX is connected to the input of the next ...
2
votes
1
answer
2k
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Convert area of ASIC into kilo-gate equivalent kGE
Is there any resource/datasheet where I can find the kilogate (kGE) of the various CMOS technologies? Essentially, I have a bunch of ASIC circuits with their areas given in mm2 that I want to convert ...
1
vote
1
answer
600
views
What topologies are used for ultra-low-power CMOS DACs?
What schematics, topologies or algorithms are suitable for ultra-low-power DAC design? You can assume the following design requirements (they are flexible):
Full custom CMOS design (this is not a ...
3
votes
3
answers
1k
views
Gate array propagation delay times
This is kind of a simple question I haven't been able to find an answer for.
According to my notes, propagation delay increases as supply voltage decreases. While intuitively I would think it would ...
4
votes
3
answers
2k
views
Understanding CMOS performance and complexity for ASIC : 350nm to 45nm process
I am trying to build an ASIC chip with the help of the MOSIS project. (They make it cheaper by combining multiple small project into a single fab). I have a choice between 350nm to 45nm, and ...