This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied.
So I come from a hardware engineering background, as I was discussing how verification is done for ASIC with a good friend of mine who specializes in software engineering out of curiosity, he posted me a question of:
How do we ensure the quality of the testbenches for verification process of chips?
From my perspective there are two things we have to consider, the first being whether the testbenches would incur some errors, the second being whether the testbenches are doing what we want them to do. In summary we need to guarantee the code correctness and functional correctness of the testbenches.
The first item can be solved at compilation stage, that is if we have errors in the code, the compiler would inform us about that.
But how about the second item?
For example, if I am using UVM framework for testing, how do I guarantee that my testbenches are written in good quality and it is designed correctly for the testing purpose?