All Questions
4
questions
2
votes
2
answers
500
views
Can the same net-list file be used for ASIC design flow as well as FPGA design flow?
I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was ...
- 182
3
votes
2
answers
17k
views
Please explain tech.lef , tech.lib
Can anyone explain what is in the tech.lef and tech lib files? Which stage of PNR (Place and Route) are they used for? Are ...
- 51
2
votes
3
answers
294
views
Routing of an ASIC chip - time taken?
In a typical ASIC design cycle, how much time is taken by an EDA tool to complete the routing?
Assume a fairly complex chip (like the Ivy Bridge). I've heard the entire chip design cycle is typically ...
- 73
7
votes
4
answers
5k
views
Getting starting designing CMOS ASIC - What is the must have software?
What software should I use to design a pipeline of gates? The design will be implemented on TSMC's 350nm process. A list of must-have software to design a basic gate circuit, and ASIC solutions would ...
- 247