All Questions
Tagged with asic digital-logic
25
questions
1
vote
0
answers
67
views
Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
0
votes
1
answer
104
views
How to do clock signal rising edge detection in Chisel (scala)?
I have encountered in a problem of rising edge detection in writing chisel code. Here is the code I wrote.
...
- 21
1
vote
1
answer
46
views
What is name of the technique where we create modules to help us test our digital design?
In my FPGA design project, I created a few modules that can be used to emulate output from another module. Then there were modules that would inject erronous data or signals that signify errors. By ...
- 12k
0
votes
1
answer
95
views
RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?
Given the below scenario, which is a reset-domain-crossing violation :
Can it be resolved using some reset synchronization strategy?
Is such design considered bad to begin with, i.e. need to avoid ...
5
votes
3
answers
2k
views
How is clock gating physically achieved inside an FPGA or ASIC?
It is bad idea to add logic gates in clock signal path. How is clock gating achieve in FPGA and ASIC designs and how does it prevent glitch in the output signal i.e the gated clock as it is enabled or ...
- 12k
3
votes
2
answers
517
views
Does the term micro-architecture have a meaning outside of microprocessors?
Wikipedia defines microarchitecture as follows:
In computer engineering, microarchitecture, also called computer
organization and sometimes abbreviated as µarch or uarch, is the way a
given ...
- 2,103
-1
votes
1
answer
169
views
Synthesis rules for this procedural assignment (combinational circuit)
I am a noob asking elementary questions. So bear with me.
If I have the following code, what would the synthesis result be if it can be synthesized at all. will the synthesizer generate intermediate ...
0
votes
1
answer
484
views
Synthesis output for the following verilog code
I have a somewhat stupid question as I am still a noob. So bear with me.
If I have the following statement in Verilog:
...
1
vote
2
answers
2k
views
ASIC gate count estimation and SRAM vs flip-flops
I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration.
Below is what I found out. Please feel free to correct, comment, expand.
Logic gates
Two ...
- 11
2
votes
2
answers
779
views
What is the proper way to reset an output signal back to zero on the next clock edge?
Occasionally writing some FPGA-targeted Verilog code at my job, I often need to drive output signals high during one clock cycle exactly. Sometimes I use the following “trick“ to achieve this (let me ...
- 259
1
vote
1
answer
161
views
What is standard coding practice for a non-blocking assignment to a large register array with variable part select in Verilog?
I couldn't find anything in the Verilog-2001 standard about this. For example, the following code works (Xilinx ISE):
...
- 111
0
votes
0
answers
60
views
Do SRAM Macros register the inputs?
In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file).
My question is this: SRAMs ...
- 143
1
vote
2
answers
1k
views
Does it make sense to use a clock input for combinational logic?
Today, I came across this problem on QuickSilicon's RTL Hackathon. It was to design an Endian converter.
The requirements were
The output should be available in the same cycle
The module should ...
- 2,331
-1
votes
1
answer
233
views
Inverter's Chain Sizing
if i have a chain of 4 identical inverters connected in series and i want to size them to obtain a specific propagation delay time, how do I approach this problem ?
i know that there are several ...
0
votes
1
answer
1k
views
Pseudo dual port RAM in verilog
How does one design a pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ?
Clarification on 'pseudo dual port - single port ...
- 109