All Questions
11
questions
0
votes
1
answer
48
views
Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
0
votes
1
answer
169
views
How does the hardware realize adding 8 values in 1 clock cycle? [closed]
For example:
result= a1+a2+a3+a4+a5+a6+a7+a8
How many adders are needed to perform this in 1 clock cycle?
What does the design look in terms of hardware?
1
vote
2
answers
1k
views
Edge aligned Source synchronous outputs
This is a basic block diagram of source synchronous interface I found in altera document.
Here
This is how edge aligned source synchronous output looks like.
They say the reciever will shift the ...
- 2,772
2
votes
1
answer
1k
views
VHDL: Optmize signal comparisons for synthesis
As a preface, there are certain coding styles used in VHDL/Verilog which help the synthesis tools infer different hardware(some better in perfomance than the other). For example using an if-else-if ...
- 53
3
votes
1
answer
4k
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Aggregate of 2 vectors in VHDL
I am checking what I can and cannot do in aggregating and concatenating in VHDL.
while I can combine two vectors by concatenating them, I keep getting error if I use aggregate.
I saw one answer here ...
- 305
3
votes
1
answer
704
views
Timing Constraints
I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
- 11k
6
votes
5
answers
4k
views
Is it good practice to always assign initial value and reset signals in digital design?
I have read that initial values to a signal can be set in an FPGA since the design is "loaded into it" after power up. However, in ASICs we can only rely on a reset signal to put all signals into a ...
- 12k
0
votes
1
answer
308
views
Some question about RTL Design and VHDL
I have some question almost uncorrelated, so I'll enureamted it, hope you can help me:
1) I'm studing RTL Design, and the question is at level of data path, arithmetic unit ecc. I don't understand ...
- 143
1
vote
1
answer
136
views
Is there an easy way to physically implement a simple digital circuit?
I designed a digital circuit which, in total, has about 27-30 gates. Building that circuit in real life using a 74 series IC would mean using a lot of through hole/SMD chips, which wouldn't be ...
- 647
2
votes
1
answer
286
views
Computational complexity of current netlist matching algorithms
I understand that the problem of matching two netlists could be reduced to the graph isomorphism problem which is NP-intermediate. Apart from that what are the complexity results of some of the ...
- 123
46
votes
2
answers
14k
views
How is ASIC design different from FPGA HDL synthesis?
I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA.
I've ...
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