I am implementing an ASIC design, and my current solution for a problem requires an SR latch. I've always been told that latches are bad in FPGA and ASIC designs, but never got a proper answer as to why. After doing some research, I found out that most modern FPGAs have the ability to use some of their registers as latches (like in the Spartan-6 serie), and that most ASIC cell libraries have latches cells.
I'm guessing that involontarily inferred latches are bad, but intended ones aren't if used properly. They can reduce testability in ASICs and could cause problems in timing analysis, but aren't fundamentally bad.
But I've read somewhere (Intel's website if I recall correctly, but I can't find it again) that SR latches can cause glitches and stability issues. There was something about NOR/NAND loops which create problems. No further information where provided so I don't understand why this would be the case. Are SR latches really a bad idea in an asynchronous ASIC design? Or is this just a general "don't use latches" recommendation?
In my design, instead of using two NOR I manually instantiated a D latch with set and reset, and grounded D and EN.