All Questions
25
questions
0
votes
1
answer
48
views
Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
-1
votes
1
answer
169
views
Synthesis rules for this procedural assignment (combinational circuit)
I am a noob asking elementary questions. So bear with me.
If I have the following code, what would the synthesis result be if it can be synthesized at all. will the synthesizer generate intermediate ...
0
votes
1
answer
484
views
Synthesis output for the following verilog code
I have a somewhat stupid question as I am still a noob. So bear with me.
If I have the following statement in Verilog:
...
1
vote
1
answer
635
views
behavior of a pipelined divider
Divider can be made combinational, which uses more logic gates..
Divider can be made sequential, the throughput may stay the same, i.e. use as many stages
as the width of the dividend (assuming width ...
2
votes
2
answers
779
views
What is the proper way to reset an output signal back to zero on the next clock edge?
Occasionally writing some FPGA-targeted Verilog code at my job, I often need to drive output signals high during one clock cycle exactly. Sometimes I use the following “trick“ to achieve this (let me ...
- 259
1
vote
1
answer
161
views
What is standard coding practice for a non-blocking assignment to a large register array with variable part select in Verilog?
I couldn't find anything in the Verilog-2001 standard about this. For example, the following code works (Xilinx ISE):
...
- 111
1
vote
0
answers
487
views
SystemVerilog: copy a slice from a vector to another vector of different size
as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location.
Example:
...
- 193
0
votes
1
answer
1k
views
Pseudo dual port RAM in verilog
How does one design a pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ?
Clarification on 'pseudo dual port - single port ...
- 109
0
votes
1
answer
204
views
How does assignment work in Verilog?
I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
1
vote
1
answer
2k
views
Generate clock jitter in a testbench
How would you generate clock jitter in a testbench?
I have seen these two ways, but I am not sure if they are the best ways:
...
- 213
0
votes
2
answers
2k
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Single Clock FIFO with Single Port RAM
I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
0
votes
1
answer
125
views
Sequence of evaluation in the following non blocking code?
I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
- 3
0
votes
1
answer
175
views
How to scale output of butterfly unit radix 2 for further stages?
I am designing 8 point FFT by radix 2 using verilog. I am using radix 2 butterfly unit with 8 bits input and so output. I expect to be 8 bit so that I can use this structure again and again for ...
- 1
0
votes
2
answers
427
views
Mixing reset and non reset registers
If you must mix synchronous reset and non reset flops in a single always block, would this be the correct way...
...
user105000
2
votes
1
answer
322
views
Is RAM with read ahead (Look ahead) possible?
Is it possible to efficiently infer a RAM with "peek" ports apart from the usual standard ports?
A 32-bit x 4 RAM might have a peek port to peek at data just ahead of the current data being accessed ...
user105000