Questions tagged [asic]
An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.
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How much does it cost to have a custom ASIC made?
I have browsed several ASIC manufacturer's webs, but I haven't found an actual number.
I assume there would be a fixed cost associated with creating masks and such and then there will be a cost per ...
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Multiple Reset Synchronization
I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
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How is ASIC design different from FPGA HDL synthesis?
I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA.
I've ...
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Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?
Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?
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Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?
There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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What are the practical uses of ASIC?
Microcontrollers, FPGAs, ASIC (Application-specific integrated circuit) all are used for similar type of applications (at different levels). I know about microcontrollers and FPGAs. But what is an ...
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Reset: synchronous vs asynchronous
I've been working with fpgas for years, and always used synchronous resets for every parts (that need it) of my circuits. It helps the circuit to be globally reset at a given clock cycle.
However, I ...
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Exotic semiconductors for fast digital ASIC
I am researching exotic semiconductors for a digital ASIC with a few million logic gates which should run as fast as possible within a $30 million budget. (Specifically, I need to do a single fully-...
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Why delays cannot be synthesized in Verilog?
I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.
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Is it good practice to always assign initial value and reset signals in digital design?
I have read that initial values to a signal can be set in an FPGA since the design is "loaded into it" after power up. However, in ASICs we can only rely on a reset signal to put all signals into a ...
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Understanding CMOS performance and complexity for ASIC : 350nm to 45nm process
I am trying to build an ASIC chip with the help of the MOSIS project. (They make it cheaper by combining multiple small project into a single fab). I have a choice between 350nm to 45nm, and ...
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What are the general steps used in creating a ASIC?
I'm following a discussion board that discusses an ASIC chip they are building, and they are using terms that I'm unfamilliar with. So far I've gathered
Once a logic design is tested on an FPGA it ...
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Advantage of clock enable over clock division
I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
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ASIC Shuttle Service Disadvantages?
Im trying to learn a bit about the techniques to create an ASIC. I found that the NRE-Costs are the biggest cost part which means the creationg of the masks and you get a minimum number of ASICs back.
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Whats the cost to create your own custom ASIC chip? [closed]
There are never any bitcoin miners available to purchase and whenever Bitmain (the leading bitcoin mining manufacturer) releases a new batch of miners they all get gobbled up in seconds. For those who ...
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