All Questions
26
questions
1
vote
0
answers
67
views
Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
1
vote
1
answer
87
views
What does ‘full custom’ really mean?
It’s common in my intro digital logic/VLSI textbooks to see mention of “full custom” chips versus ASIC chips. I’m interested in understanding the difference between the two in the context where both ...
- 1,161
0
votes
1
answer
727
views
Pin vs Port terminology in SDC
In SDC (Synopsys Design Constraints), set_driving_cell is said to be used to model the drive resistance of the cell driving the input port. I'm confused by the word ...
- 1,074
2
votes
1
answer
519
views
What are horizontal and vertical track pitches?
I was experimenting on OpenLANE with Sky130 PDK and below is the tracks.info file. I learned from a workshop that the values pertain to the track pitches as ...
- 1,074
0
votes
1
answer
95
views
RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?
Given the below scenario, which is a reset-domain-crossing violation :
Can it be resolved using some reset synchronization strategy?
Is such design considered bad to begin with, i.e. need to avoid ...
3
votes
2
answers
309
views
How do ASIC designers approach designing for extremely low supply voltages like 0.3V?
In ASIC design, there is a tradeoff between performance and energy efficiency. Since most consumer CPU's are designed for maximum performance, they operate at high voltages and clock frequencies, ...
- 147
0
votes
1
answer
480
views
Systemverilog interface definition - lint error message
I'm using Systemverilog interfaces to enable the implementation of generic functions.
The interface is defined in one file as follows:
...
- 489
1
vote
2
answers
878
views
Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?
I've been studying to understand Static Timing Analysis aka STA.
One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
- 619
0
votes
1
answer
322
views
SDC Constraints for digitally noise filtered CLOCK and DATA inputs
I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct.
I would like to know on how to make a ...
- 1
0
votes
1
answer
243
views
Respecting setup/hold time in RTL design
This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals.
In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
0
votes
2
answers
2k
views
Single Clock FIFO with Single Port RAM
I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
1
vote
2
answers
1k
views
Edge aligned Source synchronous outputs
This is a basic block diagram of source synchronous interface I found in altera document.
Here
This is how edge aligned source synchronous output looks like.
They say the reciever will shift the ...
- 2,772
3
votes
1
answer
704
views
Timing Constraints
I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
- 11k
1
vote
1
answer
839
views
Calculating resistance for metal layer from LEF File
I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278.
In the File description it is written as ...
1
vote
2
answers
2k
views
Why aren't latch based designs common these days?
Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
- 682