Questions tagged [asic]
An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.
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Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
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Is it possible to reset SRAM in one cycle?
If you have some SRAM in an ASIC and you want to reset it to 0 quickly, rather than looping over the entire memory can you just write to all words in parallel by asserting all word lines at once (this ...
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Reconciling phase shift error of length-tuned structures in 81-86GHz I/Q direct down-converter ASIC with datasheet specifications
I'm watching a video on reverse engineering a GaAs 81-86GHz I/Q down-converter ASIC. The relevant section of the video for this question is 10 minutes onwards, but watching the video isn't necessary ...
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NEC asic information from around 1990
I'm looking for datasheets with specification for the NEC ASIC/Gate Arrays from around 1990.
More preciselly, any information with specifications of their ASIC/Gate Array lines.
I would like to known ...
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SystemVerilog: copy a slice from a vector to another vector of different size
as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location.
Example:
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Power analysis using Synopsys Design Compiler
I am trying to generate power report using Synopsys DC compiler.
At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command.
Then I ...
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Area vs Operating Frequency in asic synthesis
I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in ...
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What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
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Do SRAM Macros register the inputs?
In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file).
My question is this: SRAMs ...
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Pseudo dual port RAM in verilog
How does one design a pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ?
Clarification on 'pseudo dual port - single port ...
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How does assignment work in Verilog?
I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
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What is the delay incurred by ternary content-addressable memory (TCAM)?
What is the cost (in terms of delay) of using TCAM? How do they compare with SRAM and DRAM?
I understand their use cases are different. But assume, for an application, I can do an operation using ...
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Do Broadcom's Ethernet chipsets need special software to operate?
I want to implement an Ethernet switch using Broadcom's chips. Are singing an NDA and getting the datasheets enough to work with the chips? I have heard that the chips must be programmed by a special ...
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How can I access process node data sheets?
I am searching for process node data sheets. Specifically, I'm interested in TSMC's 16nm, 12nm, 10nm, 7nm nodes, as well as Samsung's 14nm, 10nm nodes. I did not find anything with Google.
How can I ...
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Gated integrator IC, non continuous
Can anyone give me any suggestions for some good gated voltage integrators that aren't continuous, and more like a boxcar integrator? I want to integrate the the total voltage across a pulse coming ...
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