Questions tagged [system-verilog]
In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
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Can generated events get placed before events already in the event queue in SystemVerilog?
I tried to consult the Verilog LRM but wasn't successful; some of the reason is because I don't really know the correct terminology. This question is related to this one here, but I never got an ...
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Synthesizable system verilog code to find least number in an array
I have tried a few ways using for loops to find the least number in array, but having a hard time in updating the pointer whenever a new least value is encountered. I am following the below textbook ...
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How can I reduce the amount of resources I'm using in this system verilog design
I want to implement a design that follow a paper written by a researcher the part, this lead us to this picture that resume what the code I have so far is supposed to do:
As you can se the goal is to ...
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Creating entity/module containing IP from different vendors
In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly ...
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Using a parameter as a macro in system verilog code
Assume that I have below module definition with a parameter N:
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Increase operation width during the operation without extra registers in Verilog
I have two signals of type "reg" with different bit lengths:
reg [15:0] A;
reg [11:0] B;
I want to display the value of ...
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The quality of testbenches with UVM testing
This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied.
So I come from a hardware engineering background, as I was discussing how ...
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Verilog-A compiler directive inside an analog block - legal or not?
In Verilog-A, we desire to insert an `include directive inside a module and specifically inside an analog process block. Is this legal or not?
I can not find any ...
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Passing Matrices (larger arrays) between modules
I'm trying to have my design be more compartmentalized and separate each task into different modules/source files. I basically want to pass a matrix and a vector into a module I created where I'll do ...
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What is SystemVerilog way of writing the VHDL 'range attribute?
In VHDL I can write this: slv_1(slv_2'range) so that I select slice of slv_1 that has same range as ...
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doubt regarding class handle in system verilog
I am unable to understand what actually the assignment smpl=e_smpl; does. I thought that by doing so sample class handle will also point to the ext_sample but it is ...
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AMD/Xilinx SystemVerilog class variables dissapear in script vs. project simulaiton
I have asked this question on Stackoverflow but not answer yet. So, let me try EE stackexchange forum.
While scripting one of the SystemVerilog class-based testbenches I noticed that the testbench (...
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Single-Digit BCD Adder
I have this code written in SystemVerilog. The module bcdadd1 is supposed to take in two 4-bit inputs A and B and a logic input carryin (...
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QuestaSim shows internal signals of VHDL module but not SystemVerilog module
So for the first time, I created a SystemVerilog module and testbench in QuestaSim today. I created a project inside QuestaSim and then created a counter and a testbench for the counter.
When I ...
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SystemVerilog help, I'm stuck
Please help with this SystemVerilog code. The intended behavior is that the seven-segment displays 7 and 5 will show the current inputs, and the segment displays 0 and 1 will be the two-digit result ...
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