All Questions
Tagged with asic chip-design
11
questions
-1
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0
answers
40
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What kind of PLL is typically used for the digital logic in high-frequency ASIC's? [closed]
Want to generate clocks up-to 2GHz from the PLL internal to the ASIC for the critical data-path logic, please advise. Thanks!
Looks like there are wide variety of PLL's, dithered, multiphase, Fs, etc. ...
- 27
0
votes
1
answer
68
views
What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
- 137
0
votes
1
answer
112
views
Standard cell design flow in an ASIC design flow
I have a question regarding the standard cell design flow in an ASIC design flow.
That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured ...
- 103
1
vote
2
answers
2k
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ASIC gate count estimation and SRAM vs flip-flops
I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration.
Below is what I found out. Please feel free to correct, comment, expand.
Logic gates
Two ...
- 11
3
votes
3
answers
3k
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Whats the cost to create your own custom ASIC chip? [closed]
There are never any bitcoin miners available to purchase and whenever Bitmain (the leading bitcoin mining manufacturer) releases a new batch of miners they all get gobbled up in seconds. For those who ...
- 33
1
vote
2
answers
878
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Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?
I've been studying to understand Static Timing Analysis aka STA.
One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
- 619
1
vote
2
answers
346
views
CMOS technology that works above 300 °C
I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect.
Do foundries like TSMC or Globalfoundries ...
0
votes
1
answer
206
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Good practices for full-custom IC measurement? [closed]
I am a Junior Analog IC Designer and I want to characterize a full-custom IC. The thing is that I want to do it well and I don't know any reference with good practices and PCB design guidelines for ...
- 60
1
vote
4
answers
323
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Is there an "additive manufacturing" method to make an ASIC?
Reading questions like this one "How much does it cost to have a custom ASIC made?", I was wondering if there's some sort of equivalent to additive manufacturing that would lower the cost to getting ...
- 233
3
votes
2
answers
1k
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Power categories in ASIC design (Design Compiler)
I am currently working on the synthesis, with Synopsys' Design Compiler, of an AES encryption module.
In the power reports there are three power categories specified :
Switching Power
Internal Power
...
- 158
4
votes
1
answer
1k
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How do you constrain input delay for a multidimenionsal input vector?
I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...
- 43