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0 votes
1 answer
104 views

How to do clock signal rising edge detection in Chisel (scala)?

I have encountered in a problem of rising edge detection in writing chisel code. Here is the code I wrote. ...
Chenhe yuan's user avatar
0 votes
2 answers
315 views

Are SR latches bad in ASIC design?

I am implementing an ASIC design, and my current solution for a problem requires an SR latch. I've always been told that latches are bad in FPGA and ASIC designs, but never got a proper answer as to ...
Elzaidir's user avatar
  • 103
1 vote
0 answers
487 views

SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...
arandomuser's user avatar
0 votes
1 answer
204 views

How does assignment work in Verilog?

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
Karthikeya Darivemula's user avatar
-1 votes
1 answer
165 views

How is AI being used these days in designing ASIC? [closed]

Is AI used in HDL synthesis or design? For example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning. How do ...
0x90's user avatar
  • 725
0 votes
2 answers
427 views

Mixing reset and non reset registers

If you must mix synchronous reset and non reset flops in a single always block, would this be the correct way... ...
user avatar
4 votes
3 answers
392 views

Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?

I am synthesizing some multiplication units in Verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using Booth Encoding when ...
Veridian's user avatar
  • 203
195 votes
11 answers
127k views

How much does it cost to have a custom ASIC made?

I have browsed several ASIC manufacturer's webs, but I haven't found an actual number. I assume there would be a fixed cost associated with creating masks and such and then there will be a cost per ...
avakar's user avatar
  • 3,236