How to be sure that the SPICE simulation results are the exact results I will get when I build the circuit (especially an ASIC) in real?

Question

I have been doing circuit simulation in HSPICE for research. The final stage of the research is to build an ASIC. The simulation results are often satisfactory. However, I am still in doubt if the designed circuit will perform as per simulation when it is built into an ASIC. I know there are more steps to do in order to design the final ASIC (like PnR, layout, DRC, LVS, etc.). As I still haven't gone through those ASIC design steps, I am doubtful of the simulation results.

How can I be sure of the results? What are the steps I should follow (perhaps avoiding designing the chip if possible?) to be sure that the final designed chip will perform as the HSPICE simulations predict?

Answer 1

The usual process is that you obtain several SPICE model files from the foundry, each corresponding to one corner of the process variability. One model file corresponds to worst-case NMOS and worst-case PMOS, another corresponds to worst-case NMOS and best-case PMOS, and so forth.

Then you run separate simulations for all of these model files. You run separate simulations at high and low temperature. You run separate simulations at high and low supply voltage. This gives you a fairly wide range of possible behavior for your circuit.

You should expect that the actual behavior of your circuit will be somewhere in the range of behaviors that you observed for these simulations. Don't expect that the actual behavior will be exactly like any one of your various simulations.

Answer 2

Before you spin a large project, look in to Multi-Project Wafers (MPW). Many foundries have this service for their various technologies.

Hopefully, you are using models from the foundry for all your parts.

What you will do is create subcircuits which are small parts of your design and submit this to the foundry. They will combine many projects from different customers on an MPW. You can validate the SPICE simulation against an actual build. Foundries have schedules for MPW runs which means you could wait a few months, depending on when you enter the schedule cycle.

In my experience from 18 years ago, the SPICE simulations were pretty accurate using PSpice and LTspice, although, LTspice had a BSIM3 issue which Mike E. fixed the weekend it was reported.