Questions tagged [cdc]
Clock Domain Crossing. Used where information is transferred from synchronous logic from one clock source to synchronous logic using a different clock source.
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Is it possible to use a 2 flip-flop synchronizer for reset?
I have seen designs for asynchronous resets synchronization like in this picture:
I think I understand the asynchronous assertion and synchronous deassertion that this design delivers.
I am not ...
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STM32 USB Full Speed and card reading causes slow USB speed
I-m trying to accomplish best USB speed through STM32H743 MCU to PC.
First of all I was testing just receiving data. I was sending sending 8192 bytes from MCU to the pc without any other tasks, and ...
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Increase USB HS transfer rate above 100 megabits
There is a device. On board, STM32F446 + USB3315 as PHY + USB HUB assembled on USB2503. Frequency APB 180 MHz
A device project with a CDC interface has been created in CUbeMX. On command from the host,...
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Need to read USB CDC data (UART over USB) from instrument using STM32F103C8T6 Blue Pill
I have our old instrument which are showing flow over USB port using (Communication Device Class ASF Example). I am able to get data over UART 115200 using Teraterm.
I want to have this data parsed ...
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STM32 USB virtual port data sending problem
My project needs to extract sensor data from STM32, now my problem is this CDC_TRANSMIT_FS function can only send uint8_t data, I want to at least send uint16_t data or 32-bit float, how can I achieve ...
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Clock domain crossing without synchronisers
I am (re)designing an SPI slave module in VHDL for an ASIC. The SPI domain is faster than the main clock domain (~10MHz and ~1MHz), so the SPI state machine operates in the SPI domain. The previous ...
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External ADC with SPI NUCLEO-H743ZI2
I have an external ADC with a serial interface that has one data_out pin and CLK pin (16 MHz)
the data_out pin transmit 16 bits of valid data then. An all-zero pattern follows the data after all valid ...
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Do I need a clock crossing circuit for signals clocked by mirrored PLLs?
Assume that within an FPGA, I have two data streams that are being driven by two clocks. The two clocks are generated by 2 physically separated PLLs (still within the same FPGA), both of which have ...
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Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?
There are several techniques that can be used to transfer data between two asynchronous clock domains. For a few bits, and depending on direction of data between the two clock domains, one could use ...
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RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?
Given the below scenario, which is a reset-domain-crossing violation :
Can it be resolved using some reset synchronization strategy?
Is such design considered bad to begin with, i.e. need to avoid ...
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How to properly implement an n-FF synchronizer in Lattice FPGAs?
Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So ...
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How to calculate the number of required flip-flop stages needed for clock-domain crossing?
In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper ...
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What's the criterion to move from only having CDC for the control lines to include the data buses?
I've noticed that in most designs synchronized signals crossing clock domains are implemented for control signals.
I'm, however, wondering what the criteria is to add synchronization to the data bus ...
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does a 2-flip-flop synchronizer for clock domain crossing need a clear (reset) input signal?
In my current FPGA design, I have a fast clock that has to travel to multiple locations inside the device.
Among those locations, I have a set of 2-flip-flop synchronizers for clock-domain crossing ...
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Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?
Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?
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