Questions tagged [verification]
Assurance of satisfiability of all the expected requirements in either software or hardware systems.
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How can a designer be sure to authorize only legit ICs? How is performed? How are cloned ICs prevented to be activated?
The above diagram is from the IC Activation (locking/unlocking) slide of Fighting against theft, cloning and counterfeiting of integrated circuits by Lilian Bossuet Associate Professor, CNRS Chaire of ...
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Cocotb Testing with DPI in Verilator [closed]
I am testing a project using Cocotb. I now need to embed a DPI to test it further. I have created two makefiles: one for generating the .so file from my .cpp file, and another for running the ...
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The quality of testbenches with UVM testing
This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied.
So I come from a hardware engineering background, as I was discussing how ...
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How to connect multiple TLM ports to UVM Sequencer?
There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
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ESD Workstations in Manufacturing Facility
I am a manufacturing engineer for a company that just inherited a large electrical build. I am struggling to find ESD information for multiple workbenches. This is my last resort so I am hoping you ...
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Ascertaining that a BGA's decoupling capacitance is good enough
BGA parts often have a large number of power pins in the middle of the package. It is of course important to ensure that the power rail has been sufficiently capacitively decoupled. How can one go ...
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Transformer Design for a Series Resonant Converter
I am determining the Area-Product of the core required for a transformer to be used within a series resonant converter. The specifications are as follows:
Switching frequency = 400 kHz
Primary ...
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Current values verification check without ammeter [closed]
Given the following circuit with my current directions (the ones I highlighted with red):
So \$ I = - 2 A, I' = -1.5 A, I_x = \frac{1}{2} A , I_y = -1.5A , V_x = -1.5 A \$
Is this valid?
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How to use "question mark" in start method of UVM?
I am trying to modify the existing code using the start() method in UVM.
Basic code is below:
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Error while trying to bind SystemVerilog module with properties module
I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this:
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Problem overridding parametrized UVM objects
In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence '...
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When using Cocotb, should I be using FallingEdge to set and assert values?
I'm attempting to use Cooctb to verify a simple Verilog counter with a reset:
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Verification of asynchronous FIFO
I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings.
The goal is to verify this design by using the Tb components, so no UVM at all. I ...
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Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?
For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right ...
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Sign Extension in Verilog [closed]
what is the difference between the following 3 sign extensions
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