All Questions
6
questions
0
votes
1
answer
48
views
Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
2
votes
3
answers
237
views
Are FPGAs for experimentation alone?
I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
- 352
6
votes
2
answers
793
views
What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?
I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip).
On the market, there are not only regular FPGA boards, ...
- 177
0
votes
1
answer
125
views
Sequence of evaluation in the following non blocking code?
I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
- 3
2
votes
1
answer
1k
views
VHDL: Optmize signal comparisons for synthesis
As a preface, there are certain coding styles used in VHDL/Verilog which help the synthesis tools infer different hardware(some better in perfomance than the other). For example using an if-else-if ...
- 53
2
votes
2
answers
500
views
Can the same net-list file be used for ASIC design flow as well as FPGA design flow?
I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was ...
- 182