Questions tagged [vhdl]
VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.
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Latches Due to Asynchronous Load of a PISO Shift Register
What appears to be a simple problem raises a few questions regarding latches.
In trying to replicate a TI SN74HC165 PISO shift register within an iCE40UP FPGA, I've come up against a situation where a ...
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32 bit Multiplication synthesis in Quartus in VHDL on cyclone V FPGA
I encountered a strange behavior while simulating my ALU. I designed a 32-bit ALU in VHDL to perform addition, subtraction, multiplication, division, OR, AND, and XOR operations. During simulation, ...
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Weird FSM behavior on the start only
I am a vhdl beginner working on this entity that goes through 256 12bits inputs alternating with even index inputs in "a_s" and odd ones in "b_s" and this 16 inputs at a time (8 in ...
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Finding the largest std_logic_vector in an array (VHDL)
I am trying to create an output layer classifier for a neural network that is implemented on FPGA (in VHDL). The classifier should simply return the array index that contains the largest ...
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Creating entity/module containing IP from different vendors
In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly ...
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VHDL: Assert generic range and produce error with full instance path if it fails
In my VHDL entity there is a generic that has integer value. I have written an assert statement to check its range. I believe that the assert statement will execute when the module is simulated and ...
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MachXO2 VHDL Internal Oscillator - "ERROR: formal nom_freq is not declared"
I am trying to run the code below, but I get an error on line generic map(NOM_FREQ => "2.56"); and I am very confused why. The error says "ERROR - ...
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Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
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Why does the white space get included while reading a string from a file in VHDL?
I am trying to read data from a text file in VHDL which includes two vectors and single character.
While reading, white spaces are not detected for the numbers but are detected for the character.
Why ...
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Whats the error?
I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct.
Someone can tell if I'm missing something, please.
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How to correctly write and read to/from SRAM on FPGA with VHDL?
I want to write 512KByte data on SRAM(IS61/64WV512).I'm using spartan6 lx9 FPGA. In the program routine, the initial step involves writing all the data. Subsequently, upon completion of the writing ...
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Output Variable stays unintialised in my VHDL testbench
I am pretty new to VHDL and was trying to write a VHDL simulation for a simple master-slave toggle flip flop.
Following is the VHDL code that I have written:
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VHDL: Keep multiple files open until end of simulation [closed]
In my testbench I write to several outputs files as the test proceeds. These files are later processed by a Python script to generate meaningful data. The testbench writes 100,000s of lines of data in ...
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I'm trying to build a FSM in VHDL but the Mealy state machine won't change states
I'm trying to build a Mealy Finite State Machine in VHDL. each time a button 'btn' is pressed, the FSM should go to the next state. There are 4 states, s0, s1, s2 & s3. s0 is the state at which ...
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VHDL: textio variants of the write function for real data type
Here are the two variants of the write function that can be used to write the "real" data type into file or stdout.
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