Questions tagged [asic]
An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.
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What kind of PLL is typically used for the digital logic in high-frequency ASIC's? [closed]
Want to generate clocks up-to 2GHz from the PLL internal to the ASIC for the critical data-path logic, please advise. Thanks!
Looks like there are wide variety of PLL's, dithered, multiphase, Fs, etc. ...
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behavior of a pipelined divider
Divider can be made combinational, which uses more logic gates..
Divider can be made sequential, the throughput may stay the same, i.e. use as many stages
as the width of the dividend (assuming width ...
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Pseudo dual port RAM in verilog
How does one design a pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ?
Clarification on 'pseudo dual port - single port ...
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Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
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Behaviour of uninitialised RAM in an ASIC
This is a question for anyone with experience designing or with a deep knowledge of volatile memory in an ASIC. E.g. chip designers or silicon process engineers.
We are using the ET1200 EtherCAT ASIC (...
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Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
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How to scale output of butterfly unit radix 2 for further stages?
I am designing 8 point FFT by radix 2 using verilog. I am using radix 2 butterfly unit with 8 bits input and so output. I expect to be 8 bit so that I can use this structure again and again for ...
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How to be sure that the SPICE simulation results are the exact results I will get when I build the circuit (especially an ASIC) in real?
I have been doing circuit simulation in HSPICE for research. The final stage of the research is to build an ASIC. The simulation results are often satisfactory. However, I am still in doubt if the ...
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The quality of testbenches with UVM testing
This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied.
So I come from a hardware engineering background, as I was discussing how ...
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How does assignment work in Verilog?
I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
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What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
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What does ‘full custom’ really mean?
It’s common in my intro digital logic/VLSI textbooks to see mention of “full custom” chips versus ASIC chips. I’m interested in understanding the difference between the two in the context where both ...
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SDC Constraints for digitally noise filtered CLOCK and DATA inputs
I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct.
I would like to know on how to make a ...
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Standard cell design flow in an ASIC design flow
I have a question regarding the standard cell design flow in an ASIC design flow.
That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured ...
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Generate clock jitter in a testbench
How would you generate clock jitter in a testbench?
I have seen these two ways, but I am not sure if they are the best ways:
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