All Questions
23
questions
-1
votes
1
answer
169
views
Synthesis rules for this procedural assignment (combinational circuit)
I am a noob asking elementary questions. So bear with me.
If I have the following code, what would the synthesis result be if it can be synthesized at all. will the synthesizer generate intermediate ...
0
votes
1
answer
484
views
Synthesis output for the following verilog code
I have a somewhat stupid question as I am still a noob. So bear with me.
If I have the following statement in Verilog:
...
0
votes
1
answer
698
views
Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule
I have an issue in timing slack got from Design Compiler (DC.)
One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
- 17
2
votes
2
answers
779
views
What is the proper way to reset an output signal back to zero on the next clock edge?
Occasionally writing some FPGA-targeted Verilog code at my job, I often need to drive output signals high during one clock cycle exactly. Sometimes I use the following “trick“ to achieve this (let me ...
- 259
0
votes
1
answer
169
views
How does the hardware realize adding 8 values in 1 clock cycle? [closed]
For example:
result= a1+a2+a3+a4+a5+a6+a7+a8
How many adders are needed to perform this in 1 clock cycle?
What does the design look in terms of hardware?
0
votes
1
answer
322
views
SDC Constraints for digitally noise filtered CLOCK and DATA inputs
I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct.
I would like to know on how to make a ...
- 1
7
votes
1
answer
797
views
High-Level Synthesis (HLS) vs RTL for ASIC flow
I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
- 71
1
vote
2
answers
3k
views
How to constrain a clock signal out from a multiplexer
How would you constrain this design?
ext_clk and clk_in are asynchronous to each other.
clk_div is derived by clk_in with double period.
clk_out may be driven by either clk_in and ext_clk, ...
2
votes
1
answer
1k
views
VHDL: Optmize signal comparisons for synthesis
As a preface, there are certain coding styles used in VHDL/Verilog which help the synthesis tools infer different hardware(some better in perfomance than the other). For example using an if-else-if ...
- 53
3
votes
3
answers
2k
views
How is ASIC design different from FPGA design? Do you write HDL (Verilog, VHDL) to design and ASIC the same way you would for an FPGA?
From my limited understanding i feel as though one could just take the synthesis output from Verilog/VHDL code and then use that design to fabricate on silicon the sea of gates.
6
votes
1
answer
930
views
Latches and Two Phase Clocking in modern ASICs
Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
user105000
2
votes
1
answer
322
views
Is RAM with read ahead (Look ahead) possible?
Is it possible to efficiently infer a RAM with "peek" ports apart from the usual standard ports?
A 32-bit x 4 RAM might have a peek port to peek at data just ahead of the current data being accessed ...
user105000
3
votes
2
answers
1k
views
Power categories in ASIC design (Design Compiler)
I am currently working on the synthesis, with Synopsys' Design Compiler, of an AES encryption module.
In the power reports there are three power categories specified :
Switching Power
Internal Power
...
- 158
0
votes
1
answer
308
views
operand isolation in RTL
I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output ...
user105000
5
votes
4
answers
19k
views
Assigning x in verilog
Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues?
...
user105000