Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
878
questions
0
votes
1
answer
58
views
Bit Banding in STM32 CORTEX M4
I am confused in the bit banding of Cortex M4. I was going through the datasheet of STM32F446ZE and found in the memory map there was only written SRAM (112 kB aliased
By bit-banding) What does that ...
- 671
0
votes
2
answers
87
views
How does PCIe work?
I have gotten very confused with how PCIe works. I read that PCIe is a memory mapped protocol. That is, if the GPU wants to write to the CPU it will access the DDR memory located on the motherboard ...
- 97
1
vote
1
answer
75
views
Core memory output line question
How is a bit read from the core memory pictured below? I understand current through 1 and 1 vs 0 and 0 will change the torus magnets field setting a bit. I’m confused how this field is read back using ...
- 117
1
vote
1
answer
93
views
Remote update firmware for MCU
I am planning to implement a remote firmware update for my MCU and seek recommendations on the necessary features for the MCU. Specifically, I would like to understand the requirements regarding ...
- 657
2
votes
1
answer
295
views
Memory view is showing multiple bytes change after a single byte is assigned to a register. Why?
I am debugging an issue I have on a legacy codebase that is running on an atxmega32c4u chip. I am writing single bytes to registers in PORTC, but the memory view is showing multiple bytes change. The ...
- 315
0
votes
0
answers
77
views
SRAM not writing properly after radiation exposure
I have an SRAM memory device GM76C88AL with this datasheet. The RAM was exposed to a radioactive beta source (~2MeV) for some time (about 2 hours). The source was just right above it (placed on it), ...
- 1,163
1
vote
0
answers
59
views
Creating ping-pong buffer using a simple dual port RAM
In this buffer, we have two sections. Let's call these A and B. At one time we write into one but read from the other. So we write into A and read from B, or we write into B and read from A. We can ...
- 12k
0
votes
1
answer
59
views
How to access more storage?
I am doing a project with an STM32 chip. It needs to access megabytes of storage, but the chip can only access up to 32 Kilobytes of Flash memory.
Is there a way to add more memory?
0
votes
1
answer
39
views
Simplest way to interface a high-speed (125 Msps) ADC: FIFO, RAM, SerDes or FPGA
I have a 1.8 V, 125 Msps ADC (ADS4125) with an output of 12-bit parallel LVDS or CMOS. The system is operating in bursts: the data is sampled for 8 - 30 us, with a 100 ms wait time in between. I need ...
- 21
0
votes
1
answer
57
views
How to handle unused 32-bit data, dqs and dbi on DDR4 SODIMM module
In a design, I have used a DDR4 SODIMM module, which has 64-bit data, thus 8 groups of data (DQ), DQS and DBI.
However, I will only use the lower 32 bit on the module, thus have to handle the ...
- 579
1
vote
1
answer
89
views
How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
- 23
0
votes
0
answers
53
views
Weird SRAM failures when heat is applied to the system and when probed
I'm providing assistance on a project that is encountering some interesting behavior on an SRAM memory device when environmental temperature goes up or when someone probes/touches lines associated ...
- 107
6
votes
3
answers
228
views
Behaviour of uninitialised RAM in an ASIC
This is a question for anyone with experience designing or with a deep knowledge of volatile memory in an ASIC. E.g. chip designers or silicon process engineers.
We are using the ET1200 EtherCAT ASIC (...
- 27.5k
0
votes
2
answers
64
views
STM32H matrix-vector-multiply throughput
Ill be working with a board that has a STM32H743 on it, and I have a hard time reasoning about the f32 matrix-vector multiply performance I can expect of the m7 core. As I understand the core itself, ...
1
vote
1
answer
218
views
What does transfer rate in RAM actually mean? How do you actually measure it?
From what I gather, transfer rate is how many bits you transfer via the bus at once with every clock. So the formula would be: frequency (in MHz) * 2 (because of DDR) * bus width (because I think it's ...
- 41
1
vote
2
answers
69
views
Memory clock and Bus clock
The bus clock rate is how many times per second data is transferred from one component to another. If we consider DRAM DDR4-3200, the clock frequency of the RAM bus today can be 1600 MHz at the same ...
- 13
0
votes
1
answer
69
views
What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
- 137
0
votes
0
answers
27
views
What is the DDR4/5 Colum-to-Column access latency for within bank access
Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
- 324
0
votes
2
answers
95
views
Is the communication between memory controller and RAM serial?
I used to think that the communication between memory controller and RAM is parallel since we know that a RAM stick has multiple pins, just like this:
But then, from Wikipedia article on memory ...
- 443
0
votes
1
answer
159
views
How to understand Register Address, Bits, and Reset value of an electronic component?
Source: Page 31 ADXL355 MEMS' Datasheet.
Source: Page 32 ADXL355 MEMS' Datasheet
The above is some of ADXL355 Accelerometer Register map table. From that table, in the RESET column, there are their ...
- 291
1
vote
2
answers
87
views
Problem in executing the memory stage that can perform call, ret, pop, etc
I am trying to implement a Y86 processor for my college assignment.
This is my MemoryStage:
...
1
vote
2
answers
55
views
How is the structure of a matrix addressable memory block realized?
Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the ...
- 13
0
votes
1
answer
52
views
Can't write to status register of SST25VF010A flash memory
I'm having trouble writing to the status register of a SST25VF010A-33-4I-SAE 1Mbit SPI flash memory on a board I recently made. I'm using an STM32F401CBU6 to communicate with the memory.
I can read ...
- 445
1
vote
0
answers
168
views
Picking the best memory technology for our needs
This is my first post here, but bear with me. I have come here after searching the internet for a while (like most of us do)
We are in the process of figuring out which memory option would be the best ...
- 402
0
votes
0
answers
56
views
What do NRAM cells look like?
Note: I don't have any electrical engineering experience, so I'd like to apologize for my bad vocabulary about this subject.
I'm currently exploring the memory world and stumbled across NRAM which got ...
- 101
0
votes
2
answers
95
views
Why memory cell basis is typically "paired inverters" and not "paired forwarders", revisited
I asked over a year ago (link) about why memory cells typically use paired inverters instead of paired buffers. The answer mentioned gain, "this is basically because it's hard to make non-...
- 461
1
vote
2
answers
184
views
Why do AVR microprocessors have two ways (paths) to access I/O ports?
I've an ATmega328P.
Register Summary Page 275 ATmega328P datasheet.
The first address is the I/O address, and the second is the data memory address.
I'm going to set all (D ports) Data Direction ...
- 27
7
votes
2
answers
2k
views
What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?
I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
- 73
9
votes
2
answers
617
views
What is the theoretical maximum capacity of 72-pin RAM modules?
I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect.
This is my current understanding:
A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For ...
- 1,097
0
votes
1
answer
120
views
STM32H7 QuadSPI CMSIS Read
So, I am trying to access an APS6404 IC (PSRAM) with QSPI on STM32H7 (currently in single-line mode). When I am writing to it, everything seems fine, but as soon as I read - the FIFO is empty and the ...
- 1,109