Questions tagged [eda]
Electronic design automation (EDA) tools are software packages to assist with electronic design. Common examples include schematic capture, PCB design, circuit anaylsis and chip level design tools.
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How can I determine how much power is in a frequency range via FFT in LTspice?
When using LTspice, I can see the FFT of a voltage. How can I see how much power is in a particular frequency band, and what portion of the total power it is?
The FFT in LTspice is in dB, but it's ...
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How to best use Micro-Cap?
Several users of this site recommended I switch to Micro-Cap for simulation. I'm having trouble with their schematic capture:
First, the symbols are very small compared to the text. Is there a way ...
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Questa instantiation during testbench issues
I'm new to EDA and trying to get the hang of simulations in Questa. I wrote the Verilog code "clock_divider" and the testbench "tb_clock_divider". They both compile successfully ...
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Help on LM324 SUBCKT model [closed]
I'm newbie in ngspice and having a hard time to understand the LM324 models downloaded from various sources.
Made an example with 4 different instances to demonstrate my doubt.
The idealOpAmp works as ...
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What is this weird split circle symbol in a schematic?
I saw this weird symbol in a schematic and I couldn't find what it means.
It was connected from one side to the shield and ground of a USB port.
From the other side it was connected to the ground of a ...
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PCB Design Question - Power Plane or Fat Traces for High Current
I have designed my first pcb (4 layer) and I have a question about power planes versus power traces. I am using KiCad 7. I have tested the circuitry on a proto-board.
I have a high current section (12-...
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Can I Import a Netlist Into Kicad?
I'm a VHDL guy for work, and new to Kicad, so please forgive if this question is dumb.
I find it tedious to copy and paste a lot of circuit chunks to get the large matrices of diodes, IGBT's, etc for ...
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Why do PCB designers opt for serpentine tuning and switchback tuning over spiral patterns when addressing length matching in their designs?
I am currently researching the length matching problem in the PCB EDA domain and am curious as to why tools such as Allegro and Altium primarily use accordion, trombone, and sawtooth patterns to ...
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Fatal Error during SPICE Simulation of CMOS inverter on Tanner-EDA S-EDIT
I am trying to simulate the CMOS inverter (on the Tanner EDA S-edit tool). I am getting an error as follows -
Error: Simulation file "C:\Users\Carl\AppData\Local\Temp\inv_layout_tb.tsim" ...
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How can I set two different clearances on two different layers in KiCad 6?
I have a four-layer board with a substantial 48 V section. According to IPC-2221, I can use a clearance of less than 6 mil between tracks on inner layers, but I need 24 mil clearance on the outer ...
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Trouble finding/creating footprint for a specific switch (SP10T) in KiCAD
Well, I feel that time has passed me by (guess I'm old), as the local makerspace I've been visiting don't even do chemical etching anymore & the process of manufacturing a PCB from schematic to ...
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Transferring SPICE models into Eagle
I am conscious that EDA questions may be off-topic, but I think this is a general use and operation question.
I wrote this in the context of using Fusion 360/Eagle in circuit design. I am trying to ...
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PCB design for air quality measurements
I want to make a simple PCB with the following components:
1x CO₂, humidity and temperature sensor - SCD40 (Qwiic) from Sparkfun
1x 1.3 inch OLED display I2C SSH1106 from AZDelivery
1x TinyS3 (ESP32-...
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ISO/IEC Power/Ground Symbol in schematics?
Yet again, we are debating with colleagues to choose the correct power symbols in our schematics.
Some argue that using the horizontal 4-lines symbol for GND is a misunderstanding because this is not ...
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Syntax Help: VHDL Syntax Error at *.vhd near text ["process", "behave"] expecting "if"
Problem
I'm developing a simple LED blinking system in Quartus Prime Lite 18.1 to be instantiated on a DE0-Nano development board that makes use of the Cyclone IV E generation of Intel FPGAs. To do so ...
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