Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) ...
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Understanding the rigorous definition of hold time
Consider the attached from Weste and Harris's (WH) CMOS VLSI Design. I follow all of the discussion and definitions except for the hold time definition.
Now I am familiar with the common/heuristic ...
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Why do I need multiple segments to model the RC flight time of interconnect?
Consider a problem where we are interested in computing the delay for a signal to propagate to some load capacitance after a step input on the driving logic gate, and let there be a nonnegligible ...
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Does minimizing stages necessarily give best outcome when designing circuit under a delay constraint?
In the context of digital design, a common situation is to have to design a circuit for minimum energy under a delay constraint. Suppose a given circuit can be implemented with various stages. Is it ...
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Why do we need output isolation for power-gated blocks?
In their CMOS VLSI Design, Weste and Harris give the following discussion of power gating a block of logic:
I am in particular interested in understanding the need for output isolation here. Is the ...
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Calculate Acitivity Factor in VLSI
Here is the problem:
And this is my solution: activity factor = probility output node is 1 x (1 - probility output node is 1)
Source: E., W.N.H. and Harris, D.M. (2011) CMOS VLSI Design: A circuits ...
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On different well processes (fabrication process)
My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the nature of fabricating wells in the twin-well and triple-well processes. My question here is about how we can use so few ...
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On different well processes (reasons)
My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the difference between n-well, twin-well, and triple-well processes. My question here is about the reasons why we want to &...
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Why does input threshold occur at the unique voltage at which both inverter MOSFETs are in saturation?
A relevant figure of merit for a CMOS inverter is the so-called input threshold voltage (no relationship to the threshold voltage of a given MOSFET) \$V_{inv}\$, defined as the voltage \$V_{in}\$ at ...
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Justification for equivalent gate capacitance simplification in digital circuits
A MOSFET is, in reality, a four-terminal device with capacitances between each pair of terminals:
These capacitances are, of course, the standard MOSFET intrinsic and extrinsic differential ...
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What does optimizing fabs "for throughput rather than latency" mean?
In the context of a whirlwind tour of the modern VLSI design, tapeout, and fabrication flow in their CMOS VLSI Design, Weste and Harris write the following:
Multiple chips are manufactured ...
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Why do we alternate directions between metal layers?
In their CMOS VLSI Design and in the context of a discussion about the initial stages of floorplanning/physical design, Weste and Harris write that
Another important decision during floorplanning is ...
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Why do two nonoverlapping phase completely obviate the possibility of hold time issues?
In Weste and Harris's CMOS VLSI Design, they write
In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop ...
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When working with a technology node (say 14nm), should I keep the gate lengths of the FETs strictly equal to the minimum gate length?
When doing simulations with a technology node, say 14nm, can I change the gate lengths of FETs as per my wish?
If I need a FET with 140nm gate length, should I set the gate length of the transistor ...
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What does ‘full custom’ really mean?
It’s common in my intro digital logic/VLSI textbooks to see mention of “full custom” chips versus ASIC chips. I’m interested in understanding the difference between the two in the context where both ...
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