Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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Measuring the number of pulses and updating the counter after a certain number of pulses have occured using Verilog
I am trying to build a counter using Verilog which will update itself after a certain number of pulses have been detected. For example, if I am giving a 10kHz input, after every 10 pulses have been ...
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Can we calculate leakage power after synthesis at the architectural level power analysis itself?
As I understand it, leakage power depends after implementation and not on the architectural level itself.
When I report power after synthesis in Vivado I get even the leakage power. Is this possible ...
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How does an aggressor raise/drop the voltage of the victim in crosstalk?
I have been trying to understand, intuitively and physically, how crosstalk works. If I have a net that is switching (from either LO to HI or from HI to LO) running adjacent to a static line (LO or HI)...
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Why AND-Latch based clock gate (ICG cell) is not reliable only when driving negative edge triggered FFs?
I'm reading the paper "A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability"
https://ieeexplore.ieee.org/document/8702507
It says that with AND-Latch based ICG there could ...
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CPU Dynamic voltage frequency scaling - does reducing both frequency and voltage always imply reduction in current?
Referring to the equation for dynamic power P=C·V2·f, is it always assumed that reducing voltage and frequency means a reduction in power and therefore current?
Example: let's assume for this argument ...
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RHP pole of two stage OTA
I learnt that for any amplifier (with some capacitor) if we short/open the capacitor and the polarity of gain changes, it is a sign of RHP zero.
Now, while applying the same analysis I obsevred that ...
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Why use transistors at all for building gates? Alternatively: what about sub-transistor level optimization?
I was thinking about transistor design, and how the classic AND gate is composed of two transistors in series. See this image:
Now if we look at how a transistor itself is designed we can expand the ...
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How to automatically add signals in GTKwave when opened?
I use GHDL and GTKwave to compile/simulate and see the waveform of my VHDL code. Is there any way to automatically append signals in GTKwave's signals window when opened?
The problem is that I ...
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Op-amp output error due to non-infinite open-loop gain [duplicate]
Before asking the question I would like to attach the image of the BGR regarding which I have some doubts:
From what I have read, due to the high gain of the op-amp, the two inputs of the op-amp, Va ...
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How can I design a digital circuit where the output is 5 times the input? [closed]
I tried to solve this challenge by enhancing my skills in digital circuits, but could not solve it.
How can I design a digital circuit where the input is only 2 bits and the output equals 5 times the ...
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Slew rate of two stage OTA
I have learnt two stage opamp designing from books and yourtube videos, but have always failed to understand slew rate formula which is I5/Cc(I5 is bias current of M5 and Cc is compensation capacitor)....
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RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?
Given the below scenario, which is a reset-domain-crossing violation :
Can it be resolved using some reset synchronization strategy?
Is such design considered bad to begin with, i.e. need to avoid ...
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What can procedural statements do that assignment statements cannot do in Verilog?
It seems to me that for combinational circuits assignment statements are much better and for sequential as well we can use if(clk) to run programs up to an extent, so what significant advantage does ...
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MOSFET gate area?
I have a transistor with constant Vdd voltage but my W, L parameters are decreasing - what happens to my gate area?
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Processor Design: Just how complex is a real CPU datapath?
We're doing a course on Computer Architecture, and the course project involves creating an ARM-based processor.
We're supposed to create the processor in stages, and add significant features in each ...
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