Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
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Memory clock and Bus clock
The bus clock rate is how many times per second data is transferred from one component to another. If we consider DRAM DDR4-3200, the clock frequency of the RAM bus today can be 1600 MHz at the same ...
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What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
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What is the DDR4/5 Colum-to-Column access latency for within bank access
Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
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Is the communication between memory controller and RAM serial?
I used to think that the communication between memory controller and RAM is parallel since we know that a RAM stick has multiple pins, just like this:
But then, from Wikipedia article on memory ...
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How to understand Register Address, Bits, and Reset value of an electronic component?
Source: Page 31 ADXL355 MEMS' Datasheet.
Source: Page 32 ADXL355 MEMS' Datasheet
The above is some of ADXL355 Accelerometer Register map table. From that table, in the RESET column, there are their ...
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Problem in executing the memory stage that can perform call, ret, pop, etc
I am trying to implement a Y86 processor for my college assignment.
This is my MemoryStage:
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How is the structure of a matrix addressable memory block realized?
Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the ...
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Can't write to status register of SST25VF010A flash memory
I'm having trouble writing to the status register of a SST25VF010A-33-4I-SAE 1Mbit SPI flash memory on a board I recently made. I'm using an STM32F401CBU6 to communicate with the memory.
I can read ...
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Picking the best memory technology for our needs
This is my first post here, but bear with me. I have come here after searching the internet for a while (like most of us do)
We are in the process of figuring out which memory option would be the best ...
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What do NRAM cells look like?
Note: I don't have any electrical engineering experience, so I'd like to apologize for my bad vocabulary about this subject.
I'm currently exploring the memory world and stumbled across NRAM which got ...
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Why memory cell basis is typically "paired inverters" and not "paired forwarders", revisited
I asked over a year ago (link) about why memory cells typically use paired inverters instead of paired buffers. The answer mentioned gain, "this is basically because it's hard to make non-...
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Why do AVR microprocessors have two ways (paths) to access I/O ports?
I've an ATmega328P.
Register Summary Page 275 ATmega328P datasheet.
The first address is the I/O address, and the second is the data memory address.
I'm going to set all (D ports) Data Direction ...
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What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?
I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
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What is the theoretical maximum capacity of 72-pin RAM modules?
I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect.
This is my current understanding:
A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For ...
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STM32H7 QuadSPI CMSIS Read
So, I am trying to access an APS6404 IC (PSRAM) with QSPI on STM32H7 (currently in single-line mode). When I am writing to it, everything seems fine, but as soon as I read - the FIFO is empty and the ...
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