Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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On understanding tradeoffs associated with pipeline depth
In Weste and Harris's CMOS VLSI Design, they write the following in the context of a discussion about how different levels of design abstraction interact but, to be clear, my question is about the ...
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How does MOSIS let designers “share” a mask set?
In Weste and Harris's CMOS VLSI Design, they describe MOSIS as follows:
The MOSIS service [Piña02] is a low-cost prototyping service that collects designs from academic, commercial, and government ...
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Why do we use a MUX rather than tristate buffers to implement a bus?
Consider a small digital system consisting of registers connected to a bus interconnection network. It is well-known that the output to the bus can (functionally) be implemented either with tristate ...
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Is there any problem with implementing a tristate buffer this way?
Consider the following implementation of an inverting tristate buffer in CMOS:
My textbook (Weste and Harris's CMOS VLSI Design) says that to implement a (noninverting) tristate buffer we should ...
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How does this logic gate naming convention work?
In their CMOS VLSI Design, Weste and Harris seem to use a naming convention for logic gates which I cannot quite seem to define in my head. Ill give the two examples they use and hopefully someone ...
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Why does the body effect result in these \$V_{OH}\$ and \$V_{OL}\$ values?
Consider the following circuit and discussion which come from my textbook (Brown and Varnesic Fundamentals of Digital Logic):
Of course, the exercise is to notice that NMOS and PMOS are very bad in a ...
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What is the difference between a tristate buffer and a transmission gate?
Functionally, these two "blocks" seem to do the same thing: send input to output if enabled and present high impedance Z on the output if not. However, this answer seems to suggest a ...
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What is PDN in these questions?
I don't know what PDN stands for.
Can you give me some hint to solve these problem. I'm appreciate.
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Capacitances for inverter delay calculations
In CMOS VLSI DESIGN, Neil WESTE, page 144.
"The source-to-body capacitors Csbn1 and Csbp1 have both terminals tied to constant voltages and thus do not contribute to the switching capacitance. It ...
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What is wrong with this XOR gate layout?
I am learning how to make layout for various CMOS gates in MAGIC. I tried to make layout for a 2 input XOR gate in MAGIC. To the best of my knowledge it should work fine when extracted to SPICE. But ...
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Why doesn't voltage on one terminal of a capacitor matter?
In the context of characterizing the load driven by an inverter by an effective capacitance, my textbook (CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition, by Weste and Harris) gives ...
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Why doesn't body effect place limit on number of series transistors in CMOS network?
My textbook (Weste and Harris) asks the following:
Does the body effect of a process limit the number of transistors that can be placed in series in a CMOS gate at low frequencies?
It answers with ...
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Why is length scaling equivalent to series transistors?
In what follows, I am neglecting all non-idealities. All transistors are assumed to obey the first-order, long-channel IV characteristics.
My VLSI text (Weste and Harris) claims that, given these ...
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Why do series NMOS do better than a single NMOS from a delay perspective?
My VLSI text (Weste and Harris) writes the following:
Transistors in series drop part of the voltage across each transistor and thus experience smaller fields and less velocity saturation than single ...
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Why does Backside Power Distribution work for high speed CPUs?
Several upcoming or future CMOS process nodes are said to offer some kind of backside power delivery for Silicon CMOS transistors, so the precious area in the lower metal layers is freed up for signal ...
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