How does MOSIS let designers “share” a mask set?

Question

In Weste and Harris's CMOS VLSI Design, they describe MOSIS as follows:

The MOSIS service [Piña02] is a low-cost prototyping service that collects designs from academic, commercial, and government customers and aggregates them onto one mask set to share overhead costs and generate production volumes sufficient to interest fabrication companies. MOSIS has developed a set of scalable lambda-based design rules that covers a wide range of manufacturing processes. The rules describe the minimum width to avoid breaks in a line, minimum spacing to avoid shorts between lines, and mini- mum overlap to ensure that two layers completely overlap.

I am in particular confused about how on earth it's possible to "aggregate mask sets"? What is meant by this? To be clear, this is less a question about MOSIS and more a question about how it's possible to aggregate masks. Isn't there basically a one-to-one mapping between masks and the produced chip (modulo unintended differences), and wouldn't this mean everyone using MOSIS has the exact same chip?

Answer 1

wouldn't this mean everyone using MOSIS has the exact same chip?

No, you would have several of your chips on one wafer along with several of someone else's different chips.

Consider this wafer image:

There are 7 rows of chips, where each chip is labeled "Die Area". Although each of the chips looks the same in this rough picture, imagine your chips occupy the top 3 rows, whereas someone else's chip occupy the bottom 4 rows.

This image is from University Wafer.

Answer 2

Here's the way I understand it,

"Aggregate mask sets" is not, at least in my mind, an accurate description of what goes on. Pizza mask may be more appropriate in that it implies that each user gets a piece of the wafer.

In many IC manufacturing processes, the mask is called a reticle, and contains the lines and other features that make up an IC. But, the reticle is not the same size as the wafer. It is smaller than the wafer. The reticle is stepped across the wafer n times, laying down the same pattern across the wafer in multiple places. Sort of a step-and-repeat operation.

The reticle is created by the wafer manufacturer based on CAD data supplied by the IC designer. Depending on the process and how large the chip is, the reticle may contain one copy of a vary large chip, multiple copies of the same (smaller) design or (and this is key) multiple designs.

This way multiple designs from the same design company, or multiple designs from different companies can be laid down and built on a wafer which amortizes the fixed costs of a wafer across multiple designs and/or companies.

We use this a lot when designing new MMICs (Monolithic Microwave Integrated Circuits), where it is difficult to accurately model some of the manufacturing effects that may impact RF performance. So we'll come up with a basic design of, say, an RF amplifier, then tweak some of the design parameters from one iteration to the next and send multiple designs to the IC manufacturer. They will create a reticle with all those designs on it, fab a wafer and provide the die from that wafer. So we may get 100 die each of 3 or 4 different designs, depending on the size of each die and the size of the wafer.