Questions tagged [asic]
An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.
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SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops
Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...
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Hardware to run a fixed neural network
Suppose I have a feedforward neural network and I already have decided what its directed graph, weights and activation function should be. I want a device than runs this neural network as quickly as ...
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SDC Constraints for digitally noise filtered CLOCK and DATA inputs
I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct.
I would like to know on how to make a ...
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Meaning of two NOT gates in parallel
Background -- I have in my possession a schematic for an ASIC NMOS chip developed between around 1985 until 1992. It's copyrighted and I'd rather not get into the details of of what its for, but my ...
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How does assignment work in Verilog?
I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
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How is AI being used these days in designing ASIC? [closed]
Is AI used in HDL synthesis or design? For example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning.
How do ...
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Purpose of divide-by-2 (or CLK/2) on a video pixel clock generator ICs
I've been looking into some video clock generator chips and almost all of them have a divide-by-2 or CLK/2 output pin (in addition to the normal CLK out). What would be the purpose or application for ...
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What is the delay incurred by ternary content-addressable memory (TCAM)?
What is the cost (in terms of delay) of using TCAM? How do they compare with SRAM and DRAM?
I understand their use cases are different. But assume, for an application, I can do an operation using ...
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FSM modeling when outputs are not simple functions of input and current states
All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...
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Power analysis using Synopsys Design Compiler
I am trying to generate power report using Synopsys DC compiler.
At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command.
Then I ...
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What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?
I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip).
On the market, there are not only regular FPGA boards, ...
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CMOS technology that works above 300 °C
I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect.
Do foundries like TSMC or Globalfoundries ...
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Designing ASIC Chip for Enterprise [closed]
I am new here and hope to glean some expert opinions.
I am a disabled veteran and will be starting a bitcoin mining enterprise
in the near future. I have done some research and feel that inquiring
...
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Generate clock jitter in a testbench
How would you generate clock jitter in a testbench?
I have seen these two ways, but I am not sure if they are the best ways:
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Respecting setup/hold time in RTL design
This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals.
In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
