Questions tagged [verilator]
Verilator is a translation tool which converts a subset of Verilog as well as portions of SystemVerilog into C++ or SystemC.
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When I assign a signal with x in verilog, what happend in circuit?
I want to know what happen in circuit if I assign wire_a = 2'bx1.
Actually I used a module MuxKeyWithDefault, I want to use a ...
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Combinatorial circuit testing with Verilator
I have this very basic combinational logic in file tb_shift_right.v:
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Why do we need to evaluate circuit twice when clock is low?
I have written a Verilog model for a RISC-V CPU. I am simulating it using Verilator. I have copied the generic testbench class written by Gisselquist whose tick function, responsible for creating the ...
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Quirk of simulation or quirk of Verilog?
I'm having some trouble wrapping my head around this simulation waveform output. It reproduces in both Verilator and Icarus Verilog, so I'm assuming I'm just not understanding something about Verilog. ...
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Declaring Verilog parameters with division in Verilator produces width error
I am having trouble declaring Verilog parameters with division in Verilator tool. Here's the whole module:
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SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops
Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...
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"Register is illegal in left-hand side of continuous assignment" in modelsim but not verilator
module foo (A, B, C, Y);
input A, B, C;
output Y;
reg Y;
assign Y = (A && B);
endmodule
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Forcing verilator to take loop label given in RTL
I want to force the hierarchy of signal to take the loop names given in RTL written in System Verilog.
Example:
for (genvar i=0; i<4; i++) begin: GenLabel
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How can one test that a signal is High-Z when simulating with Verilator?
Say I have this module:
module Test(
input logic a,
output logic b
);
assign output = a ? 1'bZ : 1'b1;
endmodule;
Currently, when testing the module ...
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Why does this Verilog replicator statement produce a 64 bit long wire?
I'm attempting to capture the carry out of the addition of two N bit numbers with a carry in. My code is:
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