Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
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How does DDR SDRAM increase the bandwidth without increasing the frequency at which a memory array operates?
I am reading about SDRAM, and how the bandwidth was increased with DDR optimizations. From my understanding DDR can send data at a rising and falling edge, effectively doubling the data being sent. ...
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Type of memory used to design Arbitrary Waveform Generators (AWGs)
i am interested in understanding how the design decision is taken while choosing the type of memory to be used in AWGs. My understanding is that in most AWGs, waveforms are stored in a Digital memory ...
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How can I improve this RAM implementation in VHDL?
I'm practicing for a lab exam and I'm trying to solve one from past years. I feel like I'm doing something wrong because I don't have much experience with VHDL.
Exam question
Write the VHDL code for ...
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Can I use flash memory to store application data?
Context:
I am using STM32CubeIDE 1.11.0 on Linux to program (via
ST-Link V2) my STM32f103c8t6 bluepill, boot mode is 00 ("Main Flash Memory")
I have read the whole section about it in the ...
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Transfer a received array to memory in real-time
I'm using STM32F407.
I save the data read from a microphone via the HAL_I2S_Receive_DMA API using a circular buffer. I store the received data in an ...
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How to dump firmware from a PCB with an MCU and FPGA and make sure all data is extracted successfully?
I have an old PCB that is no longer manufactured. I'd like to get the firmware out of it, but it looks like it has an MCU on it and an Altera Cyclone FPGA first generation. I'm still learning how the ...
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PIC18 I2C EEPROM interface SEN stuck high
I'm trying to get a PIC18F46K40 I2C interface to work with a M24M01-D EEPROM, however I'm having problems where my code is checking for the I2C bus to be idle before initating a start condition using ...
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EEPROM endurance from a hardware view
When data is written to the EEPROM that is identical to what is already stored, does it have any different effect on endurance than when there bits are toggles?
Is there an effect, like in flash ...
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How to verify if SDRAM alternative is a direct drop in replacement?
I'm trying to verify whether the two SDRAM chips are complete drop in replacements of each other. I've verified the footprint, electrical characteristics and various timing parameters (namely CL, tRCD,...
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How to use STM32Cube Static Stack Analyzer as an automatic compile time sanity check?
I'm currently using the STM32Cube IDE to develop a project. It automatically runs the static stack analyzer every time I compile the project, but I've found if the stack size exceeds the total RAM of ...
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In DRAM, why does the precharge operation come after the activate operation and not vice-versa?
Precharging sets the bit line voltage is set to Vdd/2. To read from a dynamic memory cell, the bit line voltage must be near Vdd/2 for the sense amplifier to amplify the data value correctly. Since ...
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Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?
Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
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RISC-V Zero Instruction Question
I have seen a table of opcodes for RISC-V instructions (for base I 32 bit ISA). I am working with a RISC-V core on FPGA and had BRAM for instructions set to all zeros.
Does anybody know what happens ...
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Does NOR flash wear occur when rewriting a bit to its same value?
The obvious answer is no. Wear is caused by discharging a memory cell (bit). If the cell is a 1 and you write a 1, the cell does not get discharged. If the cell is zero and you write a zero, the cell ...
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DDR4/DDR3 CK and CK# speed ans CLK speek
I am reading the DDR4 specification from Micron but cannot get around one thing:
When you buy RAM and it says DDR4-3200MHz, does it refer to the speed of CK and CK# pins?
I think this is not referring ...
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